[uboot-lantiq] add support for arv4518 and arv752DWP22 boards
[openwrt/svn-archive/archive.git] / package / uboot-lantiq / files / board / arcadyan / arv752DWP22 / athrs26_phy.h
1 #ifndef _ATHRS26_PHY_H
2 #define _ATHRS26_PHY_H
3
4 /*****************/
5 /* PHY Registers */
6 /*****************/
7 #define ATHR_PHY_CONTROL 0
8 #define ATHR_PHY_STATUS 1
9 #define ATHR_PHY_ID1 2
10 #define ATHR_PHY_ID2 3
11 #define ATHR_AUTONEG_ADVERT 4
12 #define ATHR_LINK_PARTNER_ABILITY 5
13 #define ATHR_AUTONEG_EXPANSION 6
14 #define ATHR_NEXT_PAGE_TRANSMIT 7
15 #define ATHR_LINK_PARTNER_NEXT_PAGE 8
16 #define ATHR_1000BASET_CONTROL 9
17 #define ATHR_1000BASET_STATUS 10
18 #define ATHR_PHY_SPEC_CONTROL 16
19 #define ATHR_PHY_SPEC_STATUS 17
20 #define ATHR_DEBUG_PORT_ADDRESS 29
21 #define ATHR_DEBUG_PORT_DATA 30
22
23 /* ATHR_PHY_CONTROL fields */
24 #define ATHR_CTRL_SOFTWARE_RESET 0x8000
25 #define ATHR_CTRL_SPEED_LSB 0x2000
26 #define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000
27 #define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200
28 #define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100
29 #define ATHR_CTRL_SPEED_MSB 0x0040
30
31 #define ATHR_RESET_DONE(phy_control) \
32 (((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0)
33
34 /* Phy status fields */
35 #define ATHR_STATUS_AUTO_NEG_DONE 0x0020
36
37 #define ATHR_AUTONEG_DONE(ip_phy_status) \
38 (((ip_phy_status) & \
39 (ATHR_STATUS_AUTO_NEG_DONE)) == \
40 (ATHR_STATUS_AUTO_NEG_DONE))
41
42 /* Link Partner ability */
43 #define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100
44 #define ATHR_LINK_100BASETX 0x0080
45 #define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040
46 #define ATHR_LINK_10BASETX 0x0020
47
48 /* Advertisement register. */
49 #define ATHR_ADVERTISE_NEXT_PAGE 0x8000
50 #define ATHR_ADVERTISE_ASYM_PAUSE 0x0800
51 #define ATHR_ADVERTISE_PAUSE 0x0400
52 #define ATHR_ADVERTISE_100FULL 0x0100
53 #define ATHR_ADVERTISE_100HALF 0x0080
54 #define ATHR_ADVERTISE_10FULL 0x0040
55 #define ATHR_ADVERTISE_10HALF 0x0020
56
57 #define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \
58 ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL)
59
60 /* 1000BASET_CONTROL */
61 #define ATHR_ADVERTISE_1000FULL 0x0200
62
63 /* Phy Specific status fields */
64 #define ATHER_STATUS_LINK_MASK 0xC000
65 #define ATHER_STATUS_LINK_SHIFT 14
66 #define ATHER_STATUS_FULL_DEPLEX 0x2000
67 #define ATHR_STATUS_LINK_PASS 0x0400
68 #define ATHR_STATUS_RESOVLED 0x0800
69
70 /*phy debug port register */
71 #define ATHER_DEBUG_SERDES_REG 5
72
73 /* Serdes debug fields */
74 #define ATHER_SERDES_BEACON 0x0100
75
76 #ifndef BOOL
77 #define BOOL int
78 #define TRUE 1
79 #define FALSE 0
80 #endif
81
82 #define sysMsDelay(_x) udelay((_x) * 1000)
83
84 #undef S26_VER_1_0
85
86 #ifdef CFG_ATHRHDR_EN
87
88 #include <net.h>
89 #define header_xmit(dev,pkt,len) dev->send(dev,pkt,len) //dev_queue_xmit(skb)
90 #define header_recv_ack(dev) dev->recv(dev) //dev_queue_xmit(skb)
91
92 typedef enum {
93 NORMAL_PACKET,
94 RESERVED0,
95 MIB_1ST,
96 RESERVED1,
97 RESERVED2,
98 READ_WRITE_REG,
99 READ_WRITE_REG_ACK,
100 RESERVED3
101 } ATHR_HDR_TYPE;
102
103 typedef struct {
104 uint16_t reserved0;
105 uint16_t priority;
106 uint16_t type ;
107 uint16_t broadcast;
108 uint16_t from_cpu;
109 uint16_t reserved1;
110 uint16_t port_num;
111 }at_header_t;
112
113 typedef struct {
114 uint64_t reg_addr;
115 uint64_t reserved0;
116 uint64_t cmd_len;
117 uint64_t reserved1;
118 uint64_t cmd;
119 uint64_t reserved2;
120 uint64_t seq_num;
121 }reg_cmd_t;
122 void athrs26_reg_init(void);
123 int header_receive_pkt(uchar *pkt);
124 void athrs26_reg_dev(struct eth_device *mac);
125
126 #endif
127
128 int athrs26_phy_is_up(int unit);
129 int athrs26_phy_is_fdx(int unit);
130 int athrs26_phy_speed(int unit);
131 BOOL athrs26_phy_setup(int unit);
132
133 #endif /* _ATHRS26_PHY_H */
134