[uboot-lantiq] add preliminary AR9 support
[openwrt/svn-archive/archive.git] / package / uboot-lantiq / files / board / infineon / easy50812 / ar9.c
1 /*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2010
6 * Thomas Langer, Ralph Hempel
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 #include <common.h>
28 #include <command.h>
29 #include <netdev.h>
30 #include <miiphy.h>
31 #include <asm/addrspace.h>
32 #include <asm/ar9.h>
33 #include <asm/reboot.h>
34 #include <asm/io.h>
35 #if defined(CONFIG_CMD_HTTPD)
36 #include <httpd.h>
37 #endif
38
39 extern ulong ifx_get_ddr_hz(void);
40 extern ulong ifx_get_cpuclk(void);
41
42 /* definitions for external PHYs / Switches */
43 /* Split values into phy address and register address */
44 #define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f)
45
46 /* IDs and registers of known external switches */
47 #define ID_SAMURAI_0 0x1020
48 #define ID_SAMURAI_1 0x0007
49 #define SAMURAI_ID_REG0 0xA0
50 #define SAMURAI_ID_REG1 0xA1
51 #define ID_TANTOS 0x2599
52
53 #define RGMII_MODE 0
54 #define MII_MODE 1
55 #define REV_MII_MODE 2
56 #define RED_MII_MODE_IC 3 /*Input clock */
57 #define RGMII_MODE_100MB 4
58 #define TURBO_REV_MII_MODE 6 /*Turbo Rev Mii mode */
59 #define RED_MII_MODE_OC 7 /*Output clock */
60 #define RGMII_MODE_10MB 8
61
62 #define mdelay(n) udelay((n)*1000)
63
64 static void ar9_sw_chip_init(u8 port, u8 mode);
65 static void ar9_enable_sw_port(u8 port, u8 state);
66 static void ar9_configure_sw_port(u8 port, u8 mode);
67 static u16 ar9_smi_reg_read(u16 reg);
68 static u16 ar9_smi_reg_write(u16 reg, u16 data);
69 static char * const name = "lq_cpe_eth";
70 static int external_switch_init(void);
71
72 void _machine_restart(void)
73 {
74 *AR9_RCU_RST_REQ |= AR9_RST_ALL;
75 }
76
77 #ifdef CONFIG_SYS_RAMBOOT
78 phys_size_t initdram(int board_type)
79 {
80 return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
81 }
82 #elif defined(CONFIG_USE_DDR_RAM)
83 phys_size_t initdram(int board_type)
84 {
85 return (CONFIG_SYS_MAX_RAM);
86 }
87 #else
88
89 static ulong max_sdram_size(void) /* per Chip Select */
90 {
91 /* The only supported SDRAM data width is 16bit.
92 */
93 #define CFG_DW 4
94
95 /* The only supported number of SDRAM banks is 4.
96 */
97 #define CFG_NB 4
98
99 ulong cfgpb0 = *AR9_SDRAM_MC_CFGPB0;
100 int cols = cfgpb0 & 0xF;
101 int rows = (cfgpb0 & 0xF0) >> 4;
102 ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
103
104 return size;
105 }
106
107 /*
108 * Check memory range for valid RAM. A simple memory test determines
109 * the actually available RAM size between addresses `base' and
110 * `base + maxsize'.
111 */
112
113 static long int dram_size(long int *base, long int maxsize)
114 {
115 volatile long int *addr;
116 ulong cnt, val;
117 ulong save[32]; /* to make test non-destructive */
118 unsigned char i = 0;
119
120 for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
121 addr = base + cnt; /* pointer arith! */
122
123 save[i++] = *addr;
124 *addr = ~cnt;
125 }
126
127 /* write 0 to base address */
128 addr = base;
129 save[i] = *addr;
130 *addr = 0;
131
132 /* check at base address */
133 if ((val = *addr) != 0) {
134 *addr = save[i];
135 return (0);
136 }
137
138 for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
139 addr = base + cnt; /* pointer arith! */
140
141 val = *addr;
142 *addr = save[--i];
143
144 if (val != (~cnt)) {
145 return (cnt * sizeof (long));
146 }
147 }
148 return (maxsize);
149 }
150
151 phys_size_t initdram(int board_type)
152 {
153 int rows, cols, best_val = *AR9_SDRAM_MC_CFGPB0;
154 ulong size, max_size = 0;
155 ulong our_address;
156
157 /* load t9 into our_address */
158 asm volatile ("move %0, $25" : "=r" (our_address) :);
159
160 /* Can't probe for RAM size unless we are running from Flash.
161 * find out whether running from DRAM or Flash.
162 */
163 if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
164 {
165 return max_sdram_size();
166 }
167
168 for (cols = 0x8; cols <= 0xC; cols++)
169 {
170 for (rows = 0xB; rows <= 0xD; rows++)
171 {
172 *AR9_SDRAM_MC_CFGPB0 = (0x14 << 8) |
173 (rows << 4) | cols;
174 size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
175 max_sdram_size());
176
177 if (size > max_size)
178 {
179 best_val = *AR9_SDRAM_MC_CFGPB0;
180 max_size = size;
181 }
182 }
183 }
184
185 *AR9_SDRAM_MC_CFGPB0 = best_val;
186 return max_size;
187 }
188 #endif
189
190 int checkboard (void)
191 {
192 unsigned long chipid = *AR9_MPS_CHIPID;
193 int part_num;
194
195 puts ("Board: ");
196
197 part_num = AR9_MPS_CHIPID_PARTNUM_GET(chipid);
198 switch (part_num)
199 {
200 case 0x16C:
201 puts("ARX188 ");
202 break;
203 case 0x16D:
204 puts("ARX168 ");
205 break;
206 case 0x16F:
207 puts("ARX182 ");
208 break;
209 case 0x170:
210 puts("GRX188 ");
211 break;
212 case 0x171:
213 puts("GRX168 ");
214 break;
215 default:
216 printf ("unknown, chip part number 0x%03X ", part_num);
217 break;
218 }
219 printf ("V1.%ld, ", AR9_MPS_CHIPID_VERSION_GET(chipid));
220
221 printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
222 printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
223
224 return 0;
225 }
226
227 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
228 int board_early_init_f(void)
229 {
230 #ifdef CONFIG_EBU_ADDSEL0
231 (*AR9_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
232 #endif
233 #ifdef CONFIG_EBU_ADDSEL1
234 (*AR9_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
235 #endif
236 #ifdef CONFIG_EBU_ADDSEL2
237 (*AR9_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
238 #endif
239 #ifdef CONFIG_EBU_ADDSEL3
240 (*AR9_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
241 #endif
242 #ifdef CONFIG_EBU_BUSCON0
243 (*AR9_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
244 #endif
245 #ifdef CONFIG_EBU_BUSCON1
246 (*AR9_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
247 #endif
248 #ifdef CONFIG_EBU_BUSCON2
249 (*AR9_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
250 #endif
251 #ifdef CONFIG_EBU_BUSCON3
252 (*AR9_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
253 #endif
254
255 return 0;
256 }
257 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
258
259 int board_eth_init(bd_t *bis)
260 {
261 #if defined(CONFIG_IFX_ETOP)
262
263 *AR9_PMU_PWDCR &= 0xFFFFEFDF;
264 *AR9_PMU_PWDCR &= ~AR9_PMU_DMA; /* enable DMA from PMU */
265
266 if (lq_eth_initialize(bis) < 0)
267 return -1;
268
269 *AR9_RCU_RST_REQ |= 1;
270 udelay(200000);
271 *AR9_RCU_RST_REQ &= (unsigned long)~1;
272 udelay(1000);
273
274 #ifdef CONFIG_EXTRA_SWITCH
275 if (external_switch_init()<0)
276 return -1;
277 #endif /* CONFIG_EXTRA_SWITCH */
278 #endif /* CONFIG_IFX_ETOP */
279
280 return 0;
281 }
282
283 static void ar9_configure_sw_port(u8 port, u8 mode)
284 {
285 if(port)
286 {
287 if (mode == 1) //MII mode
288 {
289 *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
290 *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
291 *AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0xf000)) | 0x2000;
292 *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x2000;
293 }
294 else if(mode == 2 || mode == 6) //Rev Mii mode
295 {
296 *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
297 *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
298 *AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0xf000)) & ~0x2000;
299 *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xd000;
300 }
301 }
302 else //Port 0
303 {
304 if (mode == 1) //MII mode
305 {
306 *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
307 *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
308 *AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0x0303)) | 0x0100;
309 *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0100;
310 }
311 else if(mode ==2 || mode ==6) //Rev Mii mode
312 {
313 *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
314 *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
315 *AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0x0303)) & ~0x0100;
316 *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0203;
317 }
318 }
319 }
320
321 /*
322 Call this function to place either MAC port 0 or 1 into working mode.
323 Parameters:
324 port - select ports 0 or 1.
325 state of interface : state
326 0: RGMII
327 1: MII
328 2: Rev MII
329 3: Reduce MII (input clock)
330 4: RGMII 100mb
331 5: Reserve
332 6: Turbo Rev MII
333 7: Reduce MII (output clock)
334 */
335 void ar9_enable_sw_port(u8 port, u8 state)
336 {
337 REG32(AR9_SW_GCTL0) |= 0x80000000;
338 if (port == 0)
339 {
340 REG32(AR9_SW_RGMII_CTL) &= 0xffcffc0e ;
341 //#if AR9_REFBOARD_TANTOS
342 REG32(0xbf20302c) &= 0xffff81ff;
343 REG32(0xbf20302c) |= 4<<9 ;
344 //#endif
345 REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<8;
346 if((state &0x3) == 0)
347 {
348 REG32(AR9_SW_RGMII_CTL) &= 0xfffffff3;
349 if(state == 4)
350 REG32(AR9_SW_RGMII_CTL) |= 0x4;
351 else
352 REG32(AR9_SW_RGMII_CTL) |= 0x8;
353 }
354 if(state == 6)
355 REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<20));
356 if(state == 7)
357 REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<21));
358 }
359 // *AR9_PPE32_ETOP_CFG = *AR9_PPE32_ETOP_CFG & 0xfffffffe;
360 else
361 {
362 REG32(AR9_SW_RGMII_CTL) &= 0xff303fff ;
363 REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<18;
364 if((state &0x3) == 0)
365 {
366 REG32(AR9_SW_RGMII_CTL) &= 0xffffcfff;
367 if(state == 4)
368 REG32(AR9_SW_RGMII_CTL) |= 0x1000;
369 else
370 REG32(AR9_SW_RGMII_CTL) |= 0x2000;
371 }
372 if(state == 6)
373 REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<22));
374 if(state == 7)
375 REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<23));
376 }
377 }
378
379 void pci_reset(void)
380 {
381 int i,j;
382 #define AR9_V1_PCI_RST_FIX 1
383 #if AR9_V1_PCI_RST_FIX // 5th June 2008 Add GPIO19 to control EJTAG_TRST
384 *AR9_GPIO_P1_ALTSEL0 = *AR9_GPIO_P1_ALTSEL0 & ~0x8;
385 *AR9_GPIO_P1_ALTSEL1 = *AR9_GPIO_P1_ALTSEL1 & ~0x8;
386 *AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR | 0x8;
387 *AR9_GPIO_P1_OD = *AR9_GPIO_P1_OD | 0x8;
388 *AR9_GPIO_P1_OUT = *AR9_GPIO_P1_OUT | 0x8;
389 *AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 & ~0x4000;
390 *AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~0x4000;
391 *AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | 0x4000;
392 *AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | 0x4000;
393 for(j=0;j<5;j++) {
394 *AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT & ~0x4000;
395 for(i=0;i<0x10000;i++);
396 *AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT | 0x4000;
397 for(i=0;i<0x10000;i++);
398 }
399 *AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR & ~0x4000;
400 *AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR & ~0x8;
401 #endif
402 }
403
404 static u16 ar9_smi_reg_read(u16 reg)
405 {
406 int i;
407 while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
408 REG32(AR9_SW_MDIO_CTL) = 0x8000| 0x2<<10 | ((u32) (reg&0x3ff)) ; /*0x10=MDIO_OP_READ*/
409 for(i=0;i<0x3fff;i++);
410 udelay(50);
411 while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
412 return((u16) (REG32(AR9_SW_MDIO_DATA)));
413 }
414
415 static u16 ar9_smi_reg_write(u16 reg, u16 data)
416 {
417 int i;
418 while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
419 REG32(AR9_SW_MDIO_CTL) = 0x8000| (((u32) data)<<16) | 0x01<<10 | ((u32) (reg&0x3ff)) ; /*0x01=MDIO_OP_WRITE*/
420 for(i=0;i<0x3fff;i++);
421 udelay(50);
422 return 0;
423 }
424
425 static void ar9_sw_chip_init(u8 port, u8 mode)
426 {
427 int i;
428 u16 chipid;
429
430 debug("\nsearching for switches ... ");
431
432 asm("sync");
433 pci_reset();
434
435 /* 25mhz clock out */
436 *AR9_CGU_IFCCR &= ~(3<<10);
437 *AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 | (1<<3);
438 *AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~(1<<3);
439 *AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | (1<<3);
440 *AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | (1<<3);
441 *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 & ~(1<<0);
442 *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(1<<0);
443 *AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR | (1<<0);
444 *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | (1<<0);
445
446 *AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & 0xFFFBDFDF) ;
447 *AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & ~(AR9_PMU_DMA | AR9_PMU_SWITCH));
448 *AR9_PMU_PWDCR = (*AR9_PMU_PWDCR | AR9_PMU_USB0 | AR9_PMU_USB0_P);
449
450 *AR9_GPIO_P2_OUT &= ~(1<<0);
451 asm("sync");
452
453 ar9_configure_sw_port(port, mode);
454 ar9_enable_sw_port(port, mode);
455 REG32(AR9_SW_P0_CTL) |= 0x400000; /* disable mdio polling for tantos */
456 asm("sync");
457
458 /*GPIO 55(P3.7) used as output, set high*/
459 *AR9_GPIO_P3_OD |=(1<<7);
460 *AR9_GPIO_P3_DIR |= (1<<7);
461 *AR9_GPIO_P3_ALTSEL0 &=~(1<<7);
462 *AR9_GPIO_P3_ALTSEL1 &=~(1<<7);
463 asm("sync");
464 udelay(10);
465
466 *AR9_GPIO_P3_OUT &= ~(1<<7);
467 for(i=0;i<1000;i++)
468 udelay(110);
469 *AR9_GPIO_P3_OUT |=(1<<7);
470 udelay(100);
471
472 if(port==0)
473 REG32(AR9_SW_P0_CTL) |= 0x40001;
474 else
475 REG32(AR9_SW_P1_CTL) |= 0x40001;
476
477 REG32(AR9_SW_P2_CTL) |= 0x40001;
478 REG32(AR9_SW_PMAC_HD_CTL) |= 0x40000; /* enable CRC */
479
480 *AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xc00);
481 *AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xc00);
482 *AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR | 0xc00;
483 *AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xc00;
484
485 asm("sync");
486 chipid = (unsigned short)(ar9_smi_reg_read(0x101));
487 printf("\nswitch chip id=%08x\n",chipid);
488 if (chipid != ID_TANTOS) {
489 debug("whatever detected\n");
490 ar9_smi_reg_write(0x1,0x840f);
491 ar9_smi_reg_write(0x3,0x840f);
492 ar9_smi_reg_write(0x5,0x840f);
493 ar9_smi_reg_write(0x7,0x840f);
494 ar9_smi_reg_write(0x8,0x840f);
495 ar9_smi_reg_write(0x12,0x3602);
496 #ifdef CLK_OUT2_25MHZ
497 ar9_smi_reg_write(0x33,0x4000);
498 #endif
499 } else { // Tantos switch ship
500 debug("Tantos switch detected\n");
501 ar9_smi_reg_write(0xa1,0x0004); /*port 5 force link up*/
502 ar9_smi_reg_write(0xc1,0x0004); /*port 6 force link up*/
503 ar9_smi_reg_write(0xf5,0x0BBB); /*port 4 duplex mode, flow control enable,1000Mbit/s*/
504 /*port 5 duplex mode, flow control enable, 1000Mbit/s*/
505 /*port 6 duplex mode, flow control enable, 1000Mbit/s*/
506 }
507 asm("sync");
508
509 /*reset GPHY*/
510 mdelay(200);
511 *AR9_RCU_RST_REQ |= (AR9_RCU_RST_REQ_DMA | AR9_RCU_RST_REQ_PPE) ;
512 udelay(50);
513 *AR9_GPIO_P2_OUT |= (1<<0);
514 }
515
516 static void ar9_dma_init(void)
517 {
518 /* select port */
519 *AR9_DMA_PS = 0;
520
521 /*
522 TXWGT 14:12 rw Port Weight for Transmit Direction (the default value \93001\94)
523
524 TXENDI 11:10 rw Endianness for Transmit Direction
525 Determine a byte swap between memory interface (left hand side) and
526 peripheral interface (right hand side).
527 00B B0_B1_B2_B3 No byte switching
528 01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
529 10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
530
531 RXENDI 9:8 rw Endianness for Receive Direction
532 Determine a byte swap between peripheral (left hand side) and memory
533 interface (right hand side).
534 00B B0_B1_B2_B3 No byte switching
535 01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
536 10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
537 11B B3_B2_B1_B0 B0B1B2B3 => B3B2B1B0
538
539 TXBL 5:4 rw Burst Length for Transmit Direction
540 Selects burst length for TX direction.
541 Others are reserved and will result in 2_WORDS burst length.
542 01B 2_WORDS 2 words
543 10B 4_WORDS 4 words
544 11B 8_WORDS 8 words
545
546 RXBL 3:2 rw Burst Length for Receive Direction
547 Selects burst length for RX direction.
548 Others are reserved and will result in 2_WORDS burst length.
549 01B 2_WORDS 2 words
550 10B 4_WORDS 4 words
551 11B 8_WORDS 8 words
552 */
553 *AR9_DMA_PCTRL = 0x1f28;
554 }
555
556 #ifdef CONFIG_EXTRA_SWITCH
557 static int external_switch_init(void)
558 {
559 ar9_sw_chip_init(0, RGMII_MODE);
560
561 ar9_dma_init();
562
563 return 0;
564 }
565 #endif /* CONFIG_EXTRA_SWITCH */
566
567 #if defined(CONFIG_CMD_HTTPD)
568
569 static int image_info (ulong addr)
570 {
571 void *hdr = (void *)addr;
572
573 printf ("\n## Checking Image at %08lx ...\n", addr);
574
575 switch (genimg_get_format (hdr)) {
576 case IMAGE_FORMAT_LEGACY:
577 puts (" Legacy image found\n");
578 if (!image_check_magic (hdr)) {
579 puts (" Bad Magic Number\n");
580 return 1;
581 }
582
583 if (!image_check_hcrc (hdr)) {
584 puts (" Bad Header Checksum\n");
585 return 1;
586 }
587
588 image_print_contents (hdr);
589
590 puts (" Verifying Checksum ... ");
591 if (!image_check_dcrc (hdr)) {
592 puts (" Bad Data CRC\n");
593 return 1;
594 }
595 puts ("OK\n");
596 return 0;
597 #if defined(CONFIG_FIT)
598 case IMAGE_FORMAT_FIT:
599 puts (" FIT image found\n");
600
601 if (!fit_check_format (hdr)) {
602 puts ("Bad FIT image format!\n");
603 return 1;
604 }
605
606 fit_print_contents (hdr);
607
608 if (!fit_all_image_check_hashes (hdr)) {
609 puts ("Bad hash in FIT image!\n");
610 return 1;
611 }
612
613 return 0;
614 #endif
615 default:
616 puts ("Unknown image format!\n");
617 break;
618 }
619
620 return 1;
621 }
622
623 int do_http_upgrade(const unsigned char *data, const ulong size)
624 {
625 /* check the image */
626 if(image_info(data)) {
627 return -1;
628 }
629 /* write the image to the flash */
630 puts("http ugrade ...\n");
631 return 0;
632 }
633
634 int do_http_progress(const int state)
635 {
636 /* toggle LED's here */
637 switch(state) {
638 case HTTP_PROGRESS_START:
639 puts("http start\n");
640 break;
641 case HTTP_PROGRESS_TIMEOUT:
642 break;
643 case HTTP_PROGRESS_UPLOAD_READY:
644 puts("http upload ready\n");
645 break;
646 case HTTP_PROGRESS_UGRADE_READY:
647 puts("http ugrade ready\n");
648 break;
649 case HTTP_PROGRESS_UGRADE_FAILED:
650 puts("http ugrade failed\n");
651 break;
652 }
653 return 0;
654 }
655
656 unsigned long do_http_tmp_address(void)
657 {
658 char *s = getenv ("ram_addr");
659 if (s) {
660 ulong tmp = simple_strtoul (s, NULL, 16);
661 return tmp;
662 }
663 return 0 /*0x80a00000*/;
664 }
665
666 #endif