package/uboot-lantiq/files/board/infineon/easy50812/lowlevel_bootstrap_init.S

   1 /*
   2  *  Memory sub-system initialization code for Danube board.
   3  *  Andre Messerschmidt
   4  *  Copyright (c) 2005  Infineon Technologies AG
   5  *
   6  *  Based on Inca-IP code
   7  *  Copyright (c) 2003  Wolfgang Denk <wd@denx.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27 /* History:
  28       peng liu May 25, 2006, for PLL setting after reset, 05252006
  29  */
  30 #include <config.h>
  31 #include <version.h>
  32 #include <asm/regdef.h>
  33
  34 #if defined(CONFIG_USE_DDR_RAM)
  35
  36 #if defined(CONFIG_CPU_111M_RAM_111M) || defined(CONFIG_CPU_333M_RAM_111M)
  37 #       include "ar9_ddr111_settings.h"
  38 #elif defined(CONFIG_CPU_166M_RAM_166M) || defined(CONFIG_CPU_333M_RAM_166M) || defined(CONFIG_CPU_500M_RAM_166M)
  39 #       include "ar9_ddr166_settings.h"
  40 #elif defined(CONFIG_CPU_442M_RAM_147M)
  41 #       include "ar9_ddr166_settings.h"
  42 #elif defined(CONFIG_CPU_393M_RAM_196M)
  43 #       ifdef CONFIG_ETRON_RAM
  44 #               include "etron_ddr196_settings.h"
  45 #       else
  46 #               include "ar9_ddr196_settings.h"
  47 #       endif
  48 #elif defined(CONFIG_CPU_442M_RAM_221M)
  49 #       include "ar9_ddr221_settings.h"
  50 #elif defined(CONFIG_CPU_500M_RAM_250M)
  51 #       include "ar9_ddr250_settings.h"
  52 #else
  53 #       warning "missing definition for ddr_settings.h, use default!"
  54 #       include "ar9_ddr_settings.h"
  55 #endif
  56 #endif /* CONFIG_USE_DDR_RAM */
  57
  58 #define EBU_MODUL_BASE          0xBE105300
  59 #define EBU_CLC(value)          0x0000(value)
  60 #define EBU_CON(value)          0x0010(value)
  61 #define EBU_ADDSEL0(value)      0x0020(value)
  62 #define EBU_ADDSEL1(value)      0x0024(value)
  63 #define EBU_ADDSEL2(value)      0x0028(value)
  64 #define EBU_ADDSEL3(value)      0x002C(value)
  65 #define EBU_BUSCON0(value)      0x0060(value)
  66 #define EBU_BUSCON1(value)      0x0064(value)
  67 #define EBU_BUSCON2(value)      0x0068(value)
  68 #define EBU_BUSCON3(value)      0x006C(value)
  69
  70 #define MC_MODUL_BASE           0xBF800000
  71 #define MC_ERRCAUSE(value)      0x0010(value)
  72 #define MC_ERRADDR(value)       0x0020(value)
  73 #define MC_CON(value)           0x0060(value)
  74
  75 #define MC_SRAM_ENABLE          0x00000004
  76 #define MC_SDRAM_ENABLE         0x00000002
  77 #define MC_DDRRAM_ENABLE        0x00000001
  78
  79 #define MC_SDR_MODUL_BASE       0xBF800200
  80 #define MC_IOGP(value)          0x0000(value)
  81 #define MC_CTRLENA(value)       0x0010(value)
  82 #define MC_MRSCODE(value)       0x0020(value)
  83 #define MC_CFGDW(value)         0x0030(value)
  84 #define MC_CFGPB0(value)        0x0040(value)
  85 #define MC_LATENCY(value)       0x0080(value)
  86 #define MC_TREFRESH(value)      0x0090(value)
  87 #define MC_SELFRFSH(value)      0x00A0(value)
  88
  89 #define MC_DDR_MODUL_BASE       0xBF801000
  90 #define MC_DC00(value)          0x0000(value)
  91 #define MC_DC01(value)          0x0010(value)
  92 #define MC_DC02(value)          0x0020(value)
  93 #define MC_DC03(value)          0x0030(value)
  94 #define MC_DC04(value)          0x0040(value)
  95 #define MC_DC05(value)          0x0050(value)
  96 #define MC_DC06(value)          0x0060(value)
  97 #define MC_DC07(value)          0x0070(value)
  98 #define MC_DC08(value)          0x0080(value)
  99 #define MC_DC09(value)          0x0090(value)
 100 #define MC_DC10(value)          0x00A0(value)
 101 #define MC_DC11(value)          0x00B0(value)
 102 #define MC_DC12(value)          0x00C0(value)
 103 #define MC_DC13(value)          0x00D0(value)
 104 #define MC_DC14(value)          0x00E0(value)
 105 #define MC_DC15(value)          0x00F0(value)
 106 #define MC_DC16(value)          0x0100(value)
 107 #define MC_DC17(value)          0x0110(value)
 108 #define MC_DC18(value)          0x0120(value)
 109 #define MC_DC19(value)          0x0130(value)
 110 #define MC_DC20(value)          0x0140(value)
 111 #define MC_DC21(value)          0x0150(value)
 112 #define MC_DC22(value)          0x0160(value)
 113 #define MC_DC23(value)          0x0170(value)
 114 #define MC_DC24(value)          0x0180(value)
 115 #define MC_DC25(value)          0x0190(value)
 116 #define MC_DC26(value)          0x01A0(value)
 117 #define MC_DC27(value)          0x01B0(value)
 118 #define MC_DC28(value)          0x01C0(value)
 119 #define MC_DC29(value)          0x01D0(value)
 120 #define MC_DC30(value)          0x01E0(value)
 121 #define MC_DC31(value)          0x01F0(value)
 122 #define MC_DC32(value)          0x0200(value)
 123 #define MC_DC33(value)          0x0210(value)
 124 #define MC_DC34(value)          0x0220(value)
 125 #define MC_DC35(value)          0x0230(value)
 126 #define MC_DC36(value)          0x0240(value)
 127 #define MC_DC37(value)          0x0250(value)
 128 #define MC_DC38(value)          0x0260(value)
 129 #define MC_DC39(value)          0x0270(value)
 130 #define MC_DC40(value)          0x0280(value)
 131 #define MC_DC41(value)          0x0290(value)
 132 #define MC_DC42(value)          0x02A0(value)
 133 #define MC_DC43(value)          0x02B0(value)
 134 #define MC_DC44(value)          0x02C0(value)
 135 #define MC_DC45(value)          0x02D0(value)
 136 #define MC_DC46(value)          0x02E0(value)
 137
 138 #define RCU_OFFSET  0xBF203000
 139 #define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
 140 #define RCU_STS          (RCU_OFFSET + 0x0014)
 141
 142 #define CGU_OFFSET  0xBF103000
 143 #define  PLL0_CFG     (CGU_OFFSET + 0x0004)
 144 #define  PLL1_CFG     (CGU_OFFSET + 0x0008)
 145 #define  PLL2_CFG     (CGU_OFFSET + 0x000C)
 146 #define  CGU_SYS      (CGU_OFFSET + 0x0010)
 147 #define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
 148 #define  IF_CLK       (CGU_OFFSET + 0x0018)
 149 #define  CGU_SMD      (CGU_OFFSET + 0x0020)
 150 #define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
 151 #define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
 152 #define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
 153 #define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
 154 #define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
 155 #define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
 156 #define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
 157
 158 //05252006
 159 #define  pll0_35MHz_CONFIG 0x9D861059
 160 #define  pll1_35MHz_CONFIG 0x1A260CD9
 161 #define  pll2_35MHz_CONFIG 0x8000f1e5
 162 #define  pll0_36MHz_CONFIG 0x1000125D
 163 #define  pll1_36MHz_CONFIG 0x1B1E0C99
 164 #define  pll2_36MHz_CONFIG 0x8002f2a1
 165 //05252006
 166
 167 //06063001-joelin disable the PCI CFRAME mask -start
 168 /*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
 169 But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
 170
 171 The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
 172 The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
 173 */
 174 #define PCI_CR_PR_OFFSET  0xBE105400
 175 #define PCI_CR_PCI_MOD_REG          (PCI_CR_PR_OFFSET + 0x0030)
 176 #define PCI_CONFIG_SPACE  0xB7000000
 177 #define CS_CFM          (PCI_CONFIG_SPACE + 0x6C)
 178 //06063001-joelin disable the PCI CFRAME mask -end
 179         .set    noreorder
 180
 181
 182 /*
 183  * void ebu_init(void)
 184  */
 185         .globl  ebu_init
 186         .ent    ebu_init
 187 ebu_init:
 188
 189 #if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
 190         defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
 191         defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
 192         defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
 193
 194         li      t1, EBU_MODUL_BASE
 195 #if defined(CONFIG_EBU_ADDSEL0)
 196         li      t2, CONFIG_EBU_ADDSEL0
 197         sw      t2, EBU_ADDSEL0(t1)
 198 #endif
 199 #if defined(CONFIG_EBU_ADDSEL1)
 200         li      t2, CONFIG_EBU_ADDSEL1
 201         sw      t2, EBU_ADDSEL1(t1)
 202 #endif
 203 #if defined(CONFIG_EBU_ADDSEL2)
 204         li      t2, CONFIG_EBU_ADDSEL2
 205         sw      t2, EBU_ADDSEL2(t1)
 206 #endif
 207 #if defined(CONFIG_EBU_ADDSEL3)
 208         li      t2, CONFIG_EBU_ADDSEL3
 209         sw      t2, EBU_ADDSEL3(t1)
 210 #endif
 211
 212 #if defined(CONFIG_EBU_BUSCON0)
 213         li      t2, CONFIG_EBU_BUSCON0
 214         sw      t2, EBU_BUSCON0(t1)
 215 #endif
 216 #if defined(CONFIG_EBU_BUSCON1)
 217         li      t2, CONFIG_EBU_BUSCON1
 218         sw      t2, EBU_BUSCON1(t1)
 219 #endif
 220 #if defined(CONFIG_EBU_BUSCON2)
 221         li      t2, CONFIG_EBU_BUSCON2
 222         sw      t2, EBU_BUSCON2(t1)
 223 #endif
 224 #if defined(CONFIG_EBU_BUSCON3)
 225         li      t2, CONFIG_EBU_BUSCON3
 226         sw      t2, EBU_BUSCON3(t1)
 227 #endif
 228
 229 #endif
 230
 231         j       ra
 232         nop
 233
 234         .end    ebu_init
 235
 236
 237 /*
 238  * void cgu_init(long)
 239  *
 240  * a0 has the clock value
 241  */
 242         .globl  cgu_init
 243         .ent    cgu_init
 244 cgu_init:
 245         li  t2, CGU_SYS
 246         lw  t2,0(t2)
 247         beq t2,a0,freq_up2date
 248         nop
 249
 250         li  t2, RCU_STS
 251         lw  t2, 0(t2)
 252         and t2,0x00020000
 253         beq t2,0x00020000,boot_36MHZ
 254         nop
 255 //05252006
 256         li  t1, PLL0_CFG
 257         li  t2, pll0_35MHz_CONFIG
 258         sw      t2,0(t1)
 259         li  t1, PLL1_CFG
 260         li  t2, pll1_35MHz_CONFIG
 261         sw      t2,0(t1)
 262         li  t1, PLL2_CFG
 263         li  t2, pll2_35MHz_CONFIG
 264         sw      t2,0(t1)
 265         li  t1, CGU_SYS
 266         sw      a0,0(t1)
 267         li  t1, RCU_RST_REQ
 268         li  t2, 0x40000008
 269         sw      t2,0(t1)
 270         b   wait_reset
 271         nop
 272 boot_36MHZ:
 273         li  t1, PLL0_CFG
 274         li  t2, pll0_36MHz_CONFIG
 275         sw      t2,0(t1)
 276         li  t1, PLL1_CFG
 277         li  t2, pll1_36MHz_CONFIG
 278         sw      t2,0(t1)
 279         li  t1, PLL2_CFG
 280         li  t2, pll2_36MHz_CONFIG
 281         sw      t2,0(t1)
 282         li  t1, CGU_SYS
 283         sw      a0,0(t1)
 284         li  t1, RCU_RST_REQ
 285         li  t2, 0x40000008
 286         sw      t2,0(t1)
 287 //05252006
 288
 289 wait_reset:
 290         b   wait_reset
 291         nop
 292 freq_up2date:
 293         j ra
 294         nop
 295
 296         .end    cgu_init
 297
 298 #ifndef CONFIG_USE_DDR_RAM
 299 /*
 300  * void sdram_init(long)
 301  *
 302  * a0 has the clock value
 303  */
 304         .globl  sdram_init
 305         .ent    sdram_init
 306 sdram_init:
 307
 308         /* SDRAM Initialization
 309          */
 310         li      t1, MC_MODUL_BASE
 311
 312         /* Clear Error log registers */
 313         sw      zero, MC_ERRCAUSE(t1)
 314         sw      zero, MC_ERRADDR(t1)
 315
 316         /* Enable SDRAM module in memory controller */
 317         li      t3, MC_SDRAM_ENABLE
 318         lw      t2, MC_CON(t1)
 319         or      t3, t2, t3
 320         sw      t3, MC_CON(t1)
 321
 322         li      t1, MC_SDR_MODUL_BASE
 323
 324         /* disable the controller */
 325         li      t2, 0
 326         sw      t2, MC_CTRLENA(t1)
 327
 328         li      t2, 0x822
 329         sw      t2, MC_IOGP(t1)
 330
 331         li      t2, 0x2
 332         sw      t2, MC_CFGDW(t1)
 333
 334         /* Set CAS Latency */
 335         li      t2, 0x00000020
 336         sw      t2, MC_MRSCODE(t1)
 337
 338         /* Set CS0 to SDRAM parameters */
 339         li      t2, 0x000014d8
 340         sw      t2, MC_CFGPB0(t1)
 341
 342         /* Set SDRAM latency parameters */
 343         li      t2, 0x00036325;   /* BC PC100 */
 344         sw      t2, MC_LATENCY(t1)
 345
 346         /* Set SDRAM refresh rate */
 347         li      t2, 0x00000C30
 348         sw      t2, MC_TREFRESH(t1)
 349
 350         /* Clear Power-down registers */
 351         sw      zero, MC_SELFRFSH(t1)
 352
 353         /* Finally enable the controller */
 354         li      t2, 1
 355         sw      t2, MC_CTRLENA(t1)
 356
 357         j       ra
 358         nop
 359
 360         .end    sdram_init
 361
 362 #endif /* !CONFIG_USE_DDR_RAM */
 363
 364 #ifdef CONFIG_USE_DDR_RAM
 365 /*
 366  * void ddrram_init(long)
 367  *
 368  * a0 has the clock value
 369  */
 370         .globl  ddrram_init
 371         .ent    ddrram_init
 372 ddrram_init:
 373
 374         /* DDR-DRAM Initialization
 375          */
 376         li      t1, MC_MODUL_BASE
 377
 378         /* Clear Error log registers */
 379         sw      zero, MC_ERRCAUSE(t1)
 380         sw      zero, MC_ERRADDR(t1)
 381
 382         /* Enable DDR module in memory controller */
 383         li      t3, MC_DDRRAM_ENABLE
 384         lw      t2, MC_CON(t1)
 385         or      t3, t2, t3
 386         sw      t3, MC_CON(t1)
 387
 388         li      t1, MC_DDR_MODUL_BASE
 389
 390         /* Write configuration to DDR controller registers */
 391         li      t2, MC_DC0_VALUE
 392         sw      t2, MC_DC00(t1)
 393
 394         li      t2, MC_DC1_VALUE
 395         sw      t2, MC_DC01(t1)
 396
 397         li      t2, MC_DC2_VALUE
 398         sw      t2, MC_DC02(t1)
 399
 400         li      t2, MC_DC3_VALUE
 401         sw      t2, MC_DC03(t1)
 402
 403         li      t2, MC_DC4_VALUE
 404         sw      t2, MC_DC04(t1)
 405
 406         li      t2, MC_DC5_VALUE
 407         sw      t2, MC_DC05(t1)
 408
 409         li      t2, MC_DC6_VALUE
 410         sw      t2, MC_DC06(t1)
 411
 412         li      t2, MC_DC7_VALUE
 413         sw      t2, MC_DC07(t1)
 414
 415         li      t2, MC_DC8_VALUE
 416         sw      t2, MC_DC08(t1)
 417
 418         li      t2, MC_DC9_VALUE
 419         sw      t2, MC_DC09(t1)
 420
 421         li      t2, MC_DC10_VALUE
 422         sw      t2, MC_DC10(t1)
 423
 424         li      t2, MC_DC11_VALUE
 425         sw      t2, MC_DC11(t1)
 426
 427         li      t2, MC_DC12_VALUE
 428         sw      t2, MC_DC12(t1)
 429
 430         li      t2, MC_DC13_VALUE
 431         sw      t2, MC_DC13(t1)
 432
 433         li      t2, MC_DC14_VALUE
 434         sw      t2, MC_DC14(t1)
 435
 436         li      t2, MC_DC15_VALUE
 437         sw      t2, MC_DC15(t1)
 438
 439         li      t2, MC_DC16_VALUE
 440         sw      t2, MC_DC16(t1)
 441
 442         li      t2, MC_DC17_VALUE
 443         sw      t2, MC_DC17(t1)
 444
 445         li      t2, MC_DC18_VALUE
 446         sw      t2, MC_DC18(t1)
 447
 448         li      t2, MC_DC19_VALUE
 449         sw      t2, MC_DC19(t1)
 450
 451         li      t2, MC_DC20_VALUE
 452         sw      t2, MC_DC20(t1)
 453
 454         li      t2, MC_DC21_VALUE
 455         sw      t2, MC_DC21(t1)
 456
 457         li      t2, MC_DC22_VALUE
 458         sw      t2, MC_DC22(t1)
 459
 460         li      t2, MC_DC23_VALUE
 461         sw      t2, MC_DC23(t1)
 462
 463         li      t2, MC_DC24_VALUE
 464         sw      t2, MC_DC24(t1)
 465
 466         li      t2, MC_DC25_VALUE
 467         sw      t2, MC_DC25(t1)
 468
 469         li      t2, MC_DC26_VALUE
 470         sw      t2, MC_DC26(t1)
 471
 472         li      t2, MC_DC27_VALUE
 473         sw      t2, MC_DC27(t1)
 474
 475         li      t2, MC_DC28_VALUE
 476         sw      t2, MC_DC28(t1)
 477
 478         li      t2, MC_DC29_VALUE
 479         sw      t2, MC_DC29(t1)
 480
 481         li      t2, MC_DC30_VALUE
 482         sw      t2, MC_DC30(t1)
 483
 484         li      t2, MC_DC31_VALUE
 485         sw      t2, MC_DC31(t1)
 486
 487         li      t2, MC_DC32_VALUE
 488         sw      t2, MC_DC32(t1)
 489
 490         li      t2, MC_DC33_VALUE
 491         sw      t2, MC_DC33(t1)
 492
 493         li      t2, MC_DC34_VALUE
 494         sw      t2, MC_DC34(t1)
 495
 496         li      t2, MC_DC35_VALUE
 497         sw      t2, MC_DC35(t1)
 498
 499         li      t2, MC_DC36_VALUE
 500         sw      t2, MC_DC36(t1)
 501
 502         li      t2, MC_DC37_VALUE
 503         sw      t2, MC_DC37(t1)
 504
 505         li      t2, MC_DC38_VALUE
 506         sw      t2, MC_DC38(t1)
 507
 508         li      t2, MC_DC39_VALUE
 509         sw      t2, MC_DC39(t1)
 510
 511         li      t2, MC_DC40_VALUE
 512         sw      t2, MC_DC40(t1)
 513
 514         li      t2, MC_DC41_VALUE
 515         sw      t2, MC_DC41(t1)
 516
 517         li      t2, MC_DC42_VALUE
 518         sw      t2, MC_DC42(t1)
 519
 520         li      t2, MC_DC43_VALUE
 521         sw      t2, MC_DC43(t1)
 522
 523         li      t2, MC_DC44_VALUE
 524         sw      t2, MC_DC44(t1)
 525
 526         li      t2, MC_DC45_VALUE
 527         sw      t2, MC_DC45(t1)
 528
 529         li      t2, MC_DC46_VALUE
 530         sw      t2, MC_DC46(t1)
 531
 532         li      t2, 0x00000100
 533         sw      t2, MC_DC03(t1)
 534
 535         j       ra
 536         nop
 537
 538         .end    ddrram_init
 539 #endif /* CONFIG_USE_DDR_RAM */
 540
 541         .globl  lowlevel_init
 542         .ent    lowlevel_init
 543 lowlevel_init:
 544         /* EBU, CGU and SDRAM/DDR-RAM Initialization.
 545          */
 546         move    t0, ra
 547         /* We rely on the fact that non of the following ..._init() functions
 548          * modify t0
 549          */
 550 #if defined(DDR166)
 551         /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
 552         li  a0,0xe8
 553 #elif defined(DDR133)
 554         /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
 555         li  a0,0xe9
 556 #else /* defined(DDR111) */
 557         /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
 558         li  a0,0xea
 559 #endif
 560         bal     cgu_init
 561         nop
 562
 563         bal     ebu_init
 564         nop
 565
 566 //06063001-joelin disable the PCI CFRAME mask-start
 567 #ifdef DISABLE_CFRAME
 568         li  t1, PCI_CR_PCI      //mw bf103034 80000000
 569         li  t2, 0x80000000
 570         sw      t2,0(t1)
 571
 572         li  t1, PCI_CR_PCI_MOD_REG      //mw be105430 103
 573         li  t2, 0x103
 574         sw  t2,0(t1)
 575
 576         li  t1, CS_CFM                  //mw b700006c 0
 577         li  t2, 0x00
 578         sw  t2, 0(t1)
 579
 580         li  t1, PCI_CR_PCI_MOD_REG      //mw be105430 103
 581         li  t2, 0x1000103
 582         sw  t2, 0(t1)
 583 #endif
 584 //06063001-joelin disable the PCI CFRAME mask-end
 585
 586 #ifdef CONFIG_USE_DDR_RAM
 587         bal     ddrram_init
 588         nop
 589 #else
 590         bal     sdram_init
 591         nop
 592 #endif
 593         move    ra, t0
 594         j       ra
 595         nop
 596
 597         .end    lowlevel_init