add uboot-lantiq (based on a patch contributed by Lantiq)
[openwrt/svn-archive/archive.git] / package / uboot-lantiq / files / drivers / net / ifx_etop.c
1 /*
2 * Lantiq CPE device ethernet driver.
3 * Supposed to work on Twinpass/Danube.
4 *
5 * Based on INCA-IP driver:
6 * (C) Copyright 2003-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * (C) Copyright 2010
10 * Thomas Langer, Ralph Hempel
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31 #include <common.h>
32
33 #include <malloc.h>
34 #include <net.h>
35 #include <miiphy.h>
36 #include <asm/types.h>
37 #include <asm/io.h>
38 #include <asm/addrspace.h>
39
40 #include "ifx_etop.h"
41
42 #define TX_CHAN_NO 7
43 #define RX_CHAN_NO 6
44
45 #define NUM_RX_DESC PKTBUFSRX
46 #define NUM_TX_DESC 8
47 #define TOUT_LOOP 100
48
49 typedef struct
50 {
51 union
52 {
53 struct
54 {
55 volatile u32 OWN :1;
56 volatile u32 C :1;
57 volatile u32 Sop :1;
58 volatile u32 Eop :1;
59 volatile u32 reserved :3;
60 volatile u32 Byteoffset :2;
61 volatile u32 reserve :7;
62 volatile u32 DataLen :16;
63 }field;
64
65 volatile u32 word;
66 }status;
67
68 volatile u32 DataPtr;
69 } dma_rx_descriptor_t;
70
71 typedef struct
72 {
73 union
74 {
75 struct
76 {
77 volatile u32 OWN :1;
78 volatile u32 C :1;
79 volatile u32 Sop :1;
80 volatile u32 Eop :1;
81 volatile u32 Byteoffset :5;
82 volatile u32 reserved :7;
83 volatile u32 DataLen :16;
84 }field;
85
86 volatile u32 word;
87 }status;
88
89 volatile u32 DataPtr;
90 } dma_tx_descriptor_t;
91
92 static volatile dma_rx_descriptor_t rx_des_ring[NUM_RX_DESC] __attribute__ ((aligned(8)));
93 static volatile dma_tx_descriptor_t tx_des_ring[NUM_TX_DESC] __attribute__ ((aligned(8)));
94 static int tx_num, rx_num;
95
96 static volatile IfxDMA_t *pDma = (IfxDMA_t *)CKSEG1ADDR(DANUBE_DMA_BASE);
97
98 static int lq_eth_init(struct eth_device *dev, bd_t * bis);
99 static int lq_eth_send(struct eth_device *dev, volatile void *packet,int length);
100 static int lq_eth_recv(struct eth_device *dev);
101 static void lq_eth_halt(struct eth_device *dev);
102 static void lq_eth_init_chip(void);
103 static void lq_eth_init_dma(void);
104
105 static int lq_eth_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
106 {
107 u32 timeout = 50000;
108 u32 phy, reg;
109
110 if ((phyAddr > 0x1F) || (regAddr > 0x1F) || (retVal == NULL))
111 return -1;
112
113 phy = (phyAddr & 0x1F) << 21;
114 reg = (regAddr & 0x1F) << 16;
115
116 *ETOP_MDIO_ACC = 0xC0000000 | phy | reg;
117 while ((timeout--) && (*ETOP_MDIO_ACC & 0x80000000))
118 udelay(10);
119
120 if (timeout==0) {
121 *retVal = 0;
122 return -1;
123 }
124 *retVal = *ETOP_MDIO_ACC & 0xFFFF;
125 return 0;
126 }
127
128 static int lq_eth_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data)
129 {
130 u32 timeout = 50000;
131 u32 phy, reg;
132
133 if ((phyAddr > 0x1F) || (regAddr > 0x1F))
134 return -1;
135
136 phy = (phyAddr & 0x1F) << 21;
137 reg = (regAddr & 0x1F) << 16;
138
139 *ETOP_MDIO_ACC = 0x80000000 | phy | reg | data;
140 while ((timeout--) && (*ETOP_MDIO_ACC & 0x80000000))
141 udelay(10);
142
143 if (timeout==0)
144 return -1;
145 return 0;
146 }
147
148
149 int lq_eth_initialize(bd_t * bis)
150 {
151 struct eth_device *dev;
152
153 debug("Entered lq_eth_initialize()\n");
154
155 if (!(dev = malloc (sizeof *dev))) {
156 printf("Failed to allocate memory\n");
157 return -1;
158 }
159 memset(dev, 0, sizeof(*dev));
160
161 sprintf(dev->name, "lq_cpe_eth");
162 dev->init = lq_eth_init;
163 dev->halt = lq_eth_halt;
164 dev->send = lq_eth_send;
165 dev->recv = lq_eth_recv;
166
167 eth_register(dev);
168
169 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
170 /* register mii command access routines */
171 miiphy_register(dev->name,
172 lq_eth_miiphy_read, lq_eth_miiphy_write);
173 #endif
174
175 lq_eth_init_dma();
176 lq_eth_init_chip();
177
178 return 0;
179 }
180
181 static int lq_eth_init(struct eth_device *dev, bd_t * bis)
182 {
183 int i;
184 uchar *enetaddr = dev->enetaddr;
185
186 debug("lq_eth_init %x:%x:%x:%x:%x:%x\n",
187 enetaddr[0], enetaddr[1], enetaddr[2], enetaddr[3], enetaddr[4], enetaddr[5]);
188
189 *ENET_MAC_DA0 = (enetaddr[0]<<24) + (enetaddr[1]<<16) + (enetaddr[2]<< 8) + enetaddr[3];
190 *ENET_MAC_DA1 = (enetaddr[4]<<24) + (enetaddr[5]<<16);
191 *ENETS_CFG |= 1<<28; /* enable filter for unicast packets */
192
193 tx_num=0;
194 rx_num=0;
195
196 for(i=0;i < NUM_RX_DESC; i++) {
197 dma_rx_descriptor_t * rx_desc = (dma_rx_descriptor_t *)CKSEG1ADDR(&rx_des_ring[i]);
198 rx_desc->status.word=0;
199 rx_desc->status.field.OWN=1;
200 rx_desc->status.field.DataLen=PKTSIZE_ALIGN; /* 1536 */
201 rx_desc->DataPtr=(u32)CKSEG1ADDR(NetRxPackets[i]);
202 NetRxPackets[i][0] = 0xAA;
203 }
204
205 /* Reset DMA */
206 dma_writel(dma_cs, RX_CHAN_NO);
207 dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
208 dma_writel(dma_cpoll, 0x80000040);
209 /*set descriptor base*/
210 dma_writel(dma_cdba, (u32)rx_des_ring);
211 dma_writel(dma_cdlen, NUM_RX_DESC);
212 dma_writel(dma_cie, 0);
213 dma_writel(dma_cctrl, 0x30000);
214
215 for(i=0;i < NUM_TX_DESC; i++) {
216 dma_tx_descriptor_t * tx_desc = (dma_tx_descriptor_t *)CKSEG1ADDR(&tx_des_ring[i]);
217 memset(tx_desc, 0, sizeof(tx_des_ring[0]));
218 }
219
220 dma_writel(dma_cs, TX_CHAN_NO);
221 dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
222 dma_writel(dma_cpoll, 0x80000040);
223 dma_writel(dma_cdba, (u32)tx_des_ring);
224 dma_writel(dma_cdlen, NUM_TX_DESC);
225 dma_writel(dma_cie, 0);
226 dma_writel(dma_cctrl, 0x30100);
227
228 /* turn on DMA rx & tx channel
229 */
230 dma_writel(dma_cs, RX_CHAN_NO);
231 dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1); /*reset and turn on the channel*/
232
233 return 0;
234 }
235
236 static void lq_eth_halt(struct eth_device *dev)
237 {
238 int i;
239
240 debug("lq_eth_halt()\n");
241
242 for(i=0;i<8;i++) {
243 dma_writel(dma_cs, i);
244 dma_writel(dma_cctrl, dma_readl(dma_cctrl) & ~1);/*stop the dma channel*/
245 }
246 }
247
248 static int lq_eth_send(struct eth_device *dev, volatile void *packet,int length)
249 {
250 int i;
251 int res = -1;
252 volatile dma_tx_descriptor_t * tx_desc = (dma_tx_descriptor_t *)CKSEG1ADDR(&tx_des_ring[tx_num]);
253
254 if (length <= 0) {
255 printf ("%s: bad packet size: %d\n", dev->name, length);
256 goto Done;
257 }
258
259 for(i=0; tx_desc->status.field.OWN==1; i++) {
260 if (i>=TOUT_LOOP) {
261 printf("NO Tx Descriptor...");
262 goto Done;
263 }
264 }
265
266 tx_desc->status.field.Sop=1;
267 tx_desc->status.field.Eop=1;
268 tx_desc->status.field.C=0;
269 tx_desc->DataPtr = (u32)CKSEG1ADDR(packet);
270 if (length<60)
271 tx_desc->status.field.DataLen = 60;
272 else
273 tx_desc->status.field.DataLen = (u32)length;
274
275 flush_cache((u32)packet, tx_desc->status.field.DataLen);
276 tx_desc->status.field.OWN=1;
277
278 res=length;
279 tx_num++;
280 if (tx_num==NUM_TX_DESC) tx_num=0;
281
282 dma_writel(dma_cs, TX_CHAN_NO);
283 if (!(dma_readl(dma_cctrl) & 1)) {
284 dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1);
285 }
286
287 Done:
288 return res;
289 }
290
291 static int lq_eth_recv(struct eth_device *dev)
292 {
293 int length = 0;
294 volatile dma_rx_descriptor_t * rx_desc;
295
296 rx_desc = (dma_rx_descriptor_t *)CKSEG1ADDR(&rx_des_ring[rx_num]);
297
298 if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1)) {
299 return 0;
300 }
301 length = rx_desc->status.field.DataLen;
302 if (length > 4) {
303 invalidate_dcache_range((u32)CKSEG0ADDR(rx_desc->DataPtr), (u32) CKSEG0ADDR(rx_desc->DataPtr) + length);
304 NetReceive(NetRxPackets[rx_num], length);
305 } else {
306 printf("ERROR: Invalid rx packet length.\n");
307 }
308
309 rx_desc->status.field.Sop=0;
310 rx_desc->status.field.Eop=0;
311 rx_desc->status.field.C=0;
312 rx_desc->status.field.DataLen=PKTSIZE_ALIGN;
313 rx_desc->status.field.OWN=1;
314
315 rx_num++;
316 if (rx_num == NUM_RX_DESC)
317 rx_num=0;
318
319 return length;
320 }
321
322 static void lq_eth_init_chip(void)
323 {
324 *ETOP_MDIO_CFG &= ~0x6;
325 *ENET_MAC_CFG = 0x187;
326
327 // turn on port0, set to rmii and turn off port1.
328 #ifdef CONFIG_RMII
329 *ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x0000000A;
330 #else
331 *ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x00000008;
332 #endif
333
334 *ETOP_IG_PLEN_CTRL = 0x004005EE; // set packetlen.
335 *ENET_MAC_CFG |= 1<<11; /*enable the crc*/
336 return;
337 }
338
339 static void lq_eth_init_dma(void)
340 {
341 /* Reset DMA */
342 dma_writel(dma_ctrl, dma_readl(dma_ctrl) | 1);
343 dma_writel(dma_irnen, 0);/*disable all the interrupts first*/
344
345 /* Clear Interrupt Status Register */
346 dma_writel(dma_irncr, 0xfffff);
347 /*disable all the dma interrupts*/
348 dma_writel(dma_irnen, 0);
349 /*disable channel 0 and channel 1 interrupts*/
350
351 dma_writel(dma_cs, RX_CHAN_NO);
352 dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
353 dma_writel(dma_cpoll, 0x80000040);
354 /*set descriptor base*/
355 dma_writel(dma_cdba, (u32)rx_des_ring);
356 dma_writel(dma_cdlen, NUM_RX_DESC);
357 dma_writel(dma_cie, 0);
358 dma_writel(dma_cctrl, 0x30000);
359
360 dma_writel(dma_cs, TX_CHAN_NO);
361 dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
362 dma_writel(dma_cpoll, 0x80000040);
363 dma_writel(dma_cdba, (u32)tx_des_ring);
364 dma_writel(dma_cdlen, NUM_TX_DESC);
365 dma_writel(dma_cie, 0);
366 dma_writel(dma_cctrl, 0x30100);
367 /*enable the poll function and set the poll counter*/
368 //dma_writel(DMA_CPOLL=DANUBE_DMA_POLL_EN | (DANUBE_DMA_POLL_COUNT<<4);
369 /*set port properties, enable endian conversion for switch*/
370 dma_writel(dma_ps, 0);
371 dma_writel(dma_pctrl, dma_readl(dma_pctrl) | (0xf<<8));/*enable 32 bit endian conversion*/
372
373 return;
374 }