31bfdb9b632cbf6df610718cfd57852e9e43387a
[openwrt/svn-archive/archive.git] / target / linux / adm5120-2.6 / files / arch / mips / adm5120 / memory.c
1 /*
2 * $Id$
3 *
4 * Copyright (C) 2007 OpenWrt.org
5 * Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the
19 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 * Boston, MA 02110-1301, USA.
21 *
22 */
23
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27
28 #include <asm/bootinfo.h>
29 #include <asm/addrspace.h>
30
31 #include <asm/mach-adm5120/adm5120_info.h>
32 #include <asm/mach-adm5120/adm5120_defs.h>
33 #include <asm/mach-adm5120/adm5120_switch.h>
34 #include <asm/mach-adm5120/adm5120_mpmc.h>
35
36 #define SWITCH_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))
37 #define SWITCH_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v)
38
39 #define MPMC_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))
40 #define MPMC_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v)
41
42 #if 1
43 # define mem_dbg(f, a...) printk("mem_detect: " f, ## a)
44 #else
45 # define mem_dbg(f, a...)
46 #endif
47
48 #define MEM_WR_DELAY 10000 /* 0.01 usec */
49
50 unsigned long adm5120_memsize;
51
52 static int __init mem_check_pattern(u8 *addr, unsigned long offs)
53 {
54 volatile u32 *p1 = (volatile u32 *)addr;
55 volatile u32 *p2 = (volatile u32 *)(addr+offs);
56 u32 t,u,v;
57
58 /* save original value */
59 t = *p1;
60 u = *p2;
61
62 if (t != u)
63 return 0;
64
65 v = 0x55555555;
66 if (u == v)
67 v = 0xAAAAAAAA;
68
69 mem_dbg("write 0x%08x to 0x%08lX\n", v, (unsigned long)p1);
70
71 *p1 = v;
72 mem_dbg("delay %d ns\n", MEM_WR_DELAY);
73 adm5120_ndelay(MEM_WR_DELAY);
74 u = *p2;
75
76 mem_dbg("pattern at 0x%08lX is 0x%08x\n", (unsigned long)p2, u);
77
78 /* restore original value */
79 *p1 = t;
80
81 return (v == u);
82 }
83
84 static void __init adm5120_detect_memsize(void)
85 {
86 u32 memctrl;
87 u32 size, maxsize;
88 u8 *p;
89
90 memctrl = SWITCH_READ(SWITCH_REG_MEMCTRL);
91 switch (memctrl & MEMCTRL_SDRS_MASK) {
92 case MEMCTRL_SDRS_4M:
93 maxsize = 4 << 20;
94 break;
95 case MEMCTRL_SDRS_8M:
96 maxsize = 8 << 20;
97 break;
98 case MEMCTRL_SDRS_16M:
99 maxsize = 16 << 20;
100 break;
101 default:
102 maxsize = 64 << 20;
103 break;
104 }
105
106 /* disable buffers for both SDRAM banks */
107 mem_dbg("disable buffers for both banks\n");
108 MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) & ~DC_BE);
109 MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) & ~DC_BE);
110
111 mem_dbg("checking for %08xMB chip in 1st bank\n", maxsize >> 20);
112
113 /* detect size of the 1st SDRAM bank */
114 p = (u8 *)KSEG1ADDR(0);
115 for (size = 2<<20; size <= (maxsize >> 1); size <<= 1) {
116 if (mem_check_pattern(p, size)) {
117 /* mirrored address */
118 mem_dbg("mirrored data found at offset 0x%08x\n", size);
119 break;
120 }
121 }
122
123 mem_dbg("chip size in 1st bank is %08xMB\n", size >> 20);
124 adm5120_memsize = size;
125
126 if (size != maxsize)
127 /* 2nd bank is not supported */
128 goto out;
129
130 if ((memctrl & MEMCTRL_SDR1_ENABLE) == 0)
131 /* 2nd bank is disabled */
132 goto out;
133
134 /*
135 * some bootloaders enable 2nd bank, even if the 2nd SDRAM chip
136 * are missing.
137 */
138 mem_dbg("check presence of 2nd bank\n");
139
140 p = (u8 *)KSEG1ADDR(maxsize+size-4);
141 if (mem_check_pattern(p, 0)) {
142 adm5120_memsize += size;
143 }
144
145 if (maxsize != size) {
146 /* adjusting MECTRL register */
147 memctrl &= ~(MEMCTRL_SDRS_MASK);
148 switch (size>>20) {
149 case 4:
150 memctrl |= MEMCTRL_SDRS_4M;
151 break;
152 case 8:
153 memctrl |= MEMCTRL_SDRS_8M;
154 break;
155 case 16:
156 memctrl |= MEMCTRL_SDRS_16M;
157 break;
158 default:
159 memctrl |= MEMCTRL_SDRS_64M;
160 break;
161 }
162 SWITCH_WRITE(SWITCH_REG_MEMCTRL, memctrl);
163 }
164
165 out:
166 /* reenable buffer for both SDRAM banks */
167 mem_dbg("enable buffers for both banks\n");
168 MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) | DC_BE);
169 MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) | DC_BE);
170
171 mem_dbg("%dx%08xMB memory found\n", (adm5120_memsize == size) ? 1 : 2 ,
172 size >>20);
173 }
174
175 void __init adm5120_mem_init(void)
176 {
177 adm5120_detect_memsize();
178 add_memory_region(0, adm5120_memsize, BOOT_MEM_RAM);
179 }