Preliminary ADM5120 support, marked as broken
[openwrt/svn-archive/archive.git] / target / linux / adm5120-2.6 / image / lzma-loader / src / decompress.c
1 /*
2 * LZMA compressed kernel decompressor for bcm947xx boards
3 *
4 * Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 *
21 * Please note, this was code based on the bunzip2 decompressor code
22 * by Manuel Novoa III (mjn3@codepoet.org), although the only thing left
23 * is an idea and part of original vendor code
24 *
25 *
26 * 12-Mar-2005 Mineharu Takahara <mtakahar@yahoo.com>
27 * pass actual output size to decoder (stream mode
28 * compressed input is not a requirement anymore)
29 *
30 * 24-Apr-2005 Oleg I. Vdovikin
31 * reordered functions using lds script, removed forward decl
32 *
33 */
34
35 #include "LzmaDecode.h"
36
37 #define BCM4710_FLASH 0x1fc00000 /* Flash */
38
39 #define KSEG0 0x80000000
40 #define KSEG1 0xa0000000
41
42 #define KSEG1ADDR(a) ((((unsigned)(a)) & 0x1fffffffU) | KSEG1)
43
44 #define Index_Invalidate_I 0x00
45 #define Index_Writeback_Inv_D 0x01
46
47 #define cache_unroll(base,op) \
48 __asm__ __volatile__( \
49 ".set noreorder;\n" \
50 ".set mips3;\n" \
51 "cache %1, (%0);\n" \
52 ".set mips0;\n" \
53 ".set reorder\n" \
54 : \
55 : "r" (base), \
56 "i" (op));
57
58 static __inline__ void blast_icache(unsigned long size, unsigned long lsize)
59 {
60 unsigned long start = KSEG0;
61 unsigned long end = (start + size);
62
63 while(start < end) {
64 cache_unroll(start,Index_Invalidate_I);
65 start += lsize;
66 }
67 }
68
69 static __inline__ void blast_dcache(unsigned long size, unsigned long lsize)
70 {
71 unsigned long start = KSEG0;
72 unsigned long end = (start + size);
73
74 while(start < end) {
75 cache_unroll(start,Index_Writeback_Inv_D);
76 start += lsize;
77 }
78 }
79
80 #define TRX_MAGIC 0x30524448 /* "HDR0" */
81
82 struct trx_header {
83 unsigned int magic; /* "HDR0" */
84 unsigned int len; /* Length of file including header */
85 unsigned int crc32; /* 32-bit CRC from flag_version to end of file */
86 unsigned int flag_version; /* 0:15 flags, 16:31 version */
87 unsigned int offsets[3]; /* Offsets of partitions from start of header */
88 };
89
90 /* beyound the image end, size not known in advance */
91 extern unsigned char workspace[];
92
93 unsigned int offset;
94 unsigned char *data;
95
96 /* flash access should be aligned, so wrapper is used */
97 /* read byte from the flash, all accesses are 32-bit aligned */
98 static int read_byte(void *object, unsigned char **buffer, UInt32 *bufferSize)
99 {
100 static unsigned int val;
101
102 if (((unsigned int)offset % 4) == 0) {
103 val = *(unsigned int *)data;
104 data += 4;
105 }
106
107 *bufferSize = 1;
108 *buffer = ((unsigned char *)&val) + (offset++ & 3);
109
110 return LZMA_RESULT_OK;
111 }
112
113 static __inline__ unsigned char get_byte(void)
114 {
115 unsigned char *buffer;
116 UInt32 fake;
117
118 return read_byte(0, &buffer, &fake), *buffer;
119 }
120
121 /* should be the first function */
122 void entry(unsigned long icache_size, unsigned long icache_lsize,
123 unsigned long dcache_size, unsigned long dcache_lsize)
124 {
125 unsigned int i; /* temp value */
126 unsigned int lc; /* literal context bits */
127 unsigned int lp; /* literal pos state bits */
128 unsigned int pb; /* pos state bits */
129 unsigned int osize; /* uncompressed size */
130
131 ILzmaInCallback callback;
132 callback.Read = read_byte;
133
134 uart_write_str("decompress kernel ... ");
135
136 /* look for trx header, 32-bit data access */
137 for (data = ((unsigned char *) KSEG1ADDR(BCM4710_FLASH));
138 ((struct trx_header *)data)->magic != TRX_MAGIC; data += 65536);
139
140 /* compressed kernel is in the partition 0 or 1 */
141 if (((struct trx_header *)data)->offsets[1] > 65536)
142 data += ((struct trx_header *)data)->offsets[0];
143 else
144 data += ((struct trx_header *)data)->offsets[1];
145
146 offset = 0;
147
148 /* lzma args */
149 i = get_byte();
150 lc = i % 9, i = i / 9;
151 lp = i % 5, pb = i / 5;
152
153 /* skip rest of the LZMA coder property */
154 for (i = 0; i < 4; i++)
155 get_byte();
156
157 /* read the lower half of uncompressed size in the header */
158 osize = ((unsigned int)get_byte()) +
159 ((unsigned int)get_byte() << 8) +
160 ((unsigned int)get_byte() << 16) +
161 ((unsigned int)get_byte() << 24);
162
163 /* skip rest of the header (upper half of uncompressed size) */
164 for (i = 0; i < 4; i++)
165 get_byte();
166
167 /* decompress kernel */
168 if (LzmaDecode(workspace, ~0, lc, lp, pb, &callback,
169 (unsigned char*)LOADADDR, osize, &i) == LZMA_RESULT_OK)
170 {
171 blast_dcache(dcache_size, dcache_lsize);
172 blast_icache(icache_size, icache_lsize);
173
174 /* Jump to load address */
175 uart_write_str("ok\r\n");
176 ((void (*)(void)) LOADADDR)();
177 }
178 uart_write_str("failed\r\n");
179 while (1 );
180 }
181
182 /* *********************************************************************
183 *
184 * ADM5120 UART driver File: dev_adm_uart.c
185 *
186 * This is a console device driver for an ADM5120 UART
187 *
188 *********************************************************************
189 *
190 * Copyright 2006
191 * Compex Systems. All rights reserved.
192 *
193 ********************************************************************* */
194
195 #define READCSR(r) *(volatile UInt32 *)(0xB2600000+(r))
196 #define WRITECSR(r,v) *(volatile UInt32 *)(0xB2600000+(r)) = v
197
198 #define UART_DR_REG 0x00
199 #define UART_FR_REG 0x18
200 #define UART_TX_FIFO_FULL 0x20
201
202 int uart_write(int val)
203 {
204 WRITECSR(UART_DR_REG, val);
205 while ( (READCSR(UART_FR_REG) & UART_TX_FIFO_FULL) );
206 return 0;
207 }
208
209 int uart_write_str(char * str)
210 {
211 while ( *str != 0 ) {
212 uart_write ( *str++ );
213 }
214 return 0;
215 }
216
217 int uart_write_hex(int val)
218 {
219 int i;
220 int tmp;
221
222 uart_write_str("0x");
223 for ( i=0 ; i<8 ; i++ ) {
224 tmp = (val >> ((7-i) * 4 )) & 0xf;
225 tmp = tmp < 10 ? (tmp + '0') : (tmp + 'A' - 10);
226 uart_write(tmp);
227 }
228 uart_write_str("\r\n");
229 return 0;
230 }
231