target/linux/adm5120/files/arch/mips/adm5120/common/irq.c

   1 /*
   2  *  ADM5120 specific interrupt handlers
   3  *
   4  *  Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/version.h>
  15 #include <linux/irq.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/ioport.h>
  18 #include <linux/io.h>
  19 #include <linux/bitops.h>
  20
  21 #include <asm/irq_cpu.h>
  22 #include <asm/mipsregs.h>
  23
  24 #include <asm/mach-adm5120/adm5120_defs.h>
  25
  26 static void adm5120_intc_irq_unmask(unsigned int irq);
  27 static void adm5120_intc_irq_mask(unsigned int irq);
  28 static int  adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type);
  29
  30 static inline void intc_write_reg(unsigned int reg, u32 val)
  31 {
  32         void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
  33
  34         __raw_writel(val, base + reg);
  35 }
  36
  37 static inline u32 intc_read_reg(unsigned int reg)
  38 {
  39         void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
  40
  41         return __raw_readl(base + reg);
  42 }
  43
  44 static struct irq_chip adm5120_intc_irq_chip = {
  45         .name           = "INTC",
  46         .unmask         = adm5120_intc_irq_unmask,
  47         .mask           = adm5120_intc_irq_mask,
  48         .mask_ack       = adm5120_intc_irq_mask,
  49         .set_type       = adm5120_intc_irq_set_type
  50 };
  51
  52 static struct irqaction adm5120_intc_irq_action = {
  53         .handler        = no_action,
  54         .name           = "cascade [INTC]"
  55 };
  56
  57 static void adm5120_intc_irq_unmask(unsigned int irq)
  58 {
  59         irq -= ADM5120_INTC_IRQ_BASE;
  60         intc_write_reg(INTC_REG_IRQ_ENABLE, 1 << irq);
  61 }
  62
  63 static void adm5120_intc_irq_mask(unsigned int irq)
  64 {
  65         irq -= ADM5120_INTC_IRQ_BASE;
  66         intc_write_reg(INTC_REG_IRQ_DISABLE, 1 << irq);
  67 }
  68
  69 static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type)
  70 {
  71         unsigned int sense;
  72         unsigned long mode;
  73         int err = 0;
  74
  75         sense = flow_type & (IRQ_TYPE_SENSE_MASK);
  76         switch (sense) {
  77         case IRQ_TYPE_NONE:
  78         case IRQ_TYPE_LEVEL_HIGH:
  79                 break;
  80         case IRQ_TYPE_LEVEL_LOW:
  81                 switch (irq) {
  82                 case ADM5120_IRQ_GPIO2:
  83                 case ADM5120_IRQ_GPIO4:
  84                         break;
  85                 default:
  86                         err = -EINVAL;
  87                         break;
  88                 }
  89                 break;
  90         default:
  91                 err = -EINVAL;
  92                 break;
  93         }
  94
  95         if (err)
  96                 return err;
  97
  98         switch (irq) {
  99         case ADM5120_IRQ_GPIO2:
 100         case ADM5120_IRQ_GPIO4:
 101                 mode = intc_read_reg(INTC_REG_INT_MODE);
 102                 if (sense == IRQ_TYPE_LEVEL_LOW)
 103                         mode |= (1 << (irq - ADM5120_INTC_IRQ_BASE));
 104                 else
 105                         mode &= ~(1 << (irq - ADM5120_INTC_IRQ_BASE));
 106
 107                 intc_write_reg(INTC_REG_INT_MODE, mode);
 108                 /* fallthrough */
 109         default:
 110                 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
 111                 irq_desc[irq].status |= sense;
 112                 break;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static void adm5120_intc_irq_dispatch(void)
 119 {
 120         unsigned long status;
 121         int irq;
 122
 123         status = intc_read_reg(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
 124         if (status) {
 125                 irq = ADM5120_INTC_IRQ_BASE + fls(status) - 1;
 126                 do_IRQ(irq);
 127         } else
 128                 spurious_interrupt();
 129 }
 130
 131 asmlinkage void plat_irq_dispatch(void)
 132 {
 133         unsigned long pending;
 134
 135         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 136
 137         if (pending & STATUSF_IP7)
 138                 do_IRQ(ADM5120_IRQ_COUNTER);
 139         else if (pending & STATUSF_IP2)
 140                 adm5120_intc_irq_dispatch();
 141         else
 142                 spurious_interrupt();
 143 }
 144
 145 #define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
 146 static void __init adm5120_intc_irq_init(void)
 147 {
 148         int i;
 149
 150         /* disable all interrupts */
 151         intc_write_reg(INTC_REG_IRQ_DISABLE, INTC_INT_ALL);
 152
 153         /* setup all interrupts to generate IRQ instead of FIQ */
 154         intc_write_reg(INTC_REG_INT_MODE, 0);
 155
 156         /* set active level for all external interrupts to HIGH */
 157         intc_write_reg(INTC_REG_INT_LEVEL, 0);
 158
 159         /* disable usage of the TEST_SOURCE register */
 160         intc_write_reg(INTC_REG_IRQ_SOURCE_SELECT, 0);
 161
 162         for (i = ADM5120_INTC_IRQ_BASE;
 163                 i <= ADM5120_INTC_IRQ_BASE + INTC_IRQ_LAST;
 164                 i++) {
 165                 irq_desc[i].status = INTC_IRQ_STATUS;
 166                 set_irq_chip_and_handler(i, &adm5120_intc_irq_chip,
 167                         handle_level_irq);
 168         }
 169
 170         setup_irq(ADM5120_IRQ_INTC, &adm5120_intc_irq_action);
 171 }
 172
 173 void __init arch_init_irq(void)
 174 {
 175         mips_cpu_irq_init();
 176         adm5120_intc_irq_init();
 177 }