c75b87af45404690ba17a5a4313b229d6e3285a6
[openwrt/svn-archive/archive.git] / target / linux / adm5120 / files / drivers / usb / host / adm5120-hcd.c
1 /*
2 * ADM5120 HCD (Host Controller Driver) for USB
3 *
4 * Copyright (C) 2007,2008 Gabor Juhos <juhosg at openwrt.org>
5 *
6 * This file was derived from: drivers/usb/host/ohci-hcd.c
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 *
10 * [ Initialisation is based on Linus' ]
11 * [ uhci code and gregs ahcd fragments ]
12 * [ (C) Copyright 1999 Linus Torvalds ]
13 * [ (C) Copyright 1999 Gregory P. Smith]
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License version 2 as published
17 * by the Free Software Foundation.
18 *
19 */
20
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmapool.h>
37 #include <linux/reboot.h>
38
39 #include <asm/io.h>
40 #include <asm/irq.h>
41 #include <asm/system.h>
42 #include <asm/unaligned.h>
43 #include <asm/byteorder.h>
44
45 #include "../core/hcd.h"
46 #include "../core/hub.h"
47
48 #define DRIVER_VERSION "0.16.0"
49 #define DRIVER_AUTHOR "Gabor Juhos <juhosg at openwrt.org>"
50 #define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
51
52 /*-------------------------------------------------------------------------*/
53
54 #undef ADMHC_VERBOSE_DEBUG /* not always helpful */
55
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58
59 #define ADMHC_INTR_INIT \
60 ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
61 | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
62
63 /*-------------------------------------------------------------------------*/
64
65 static const char hcd_name [] = "admhc-hcd";
66
67 #define STATECHANGE_DELAY msecs_to_jiffies(300)
68
69 #include "adm5120.h"
70
71 static void admhc_dump(struct admhcd *ahcd, int verbose);
72 static int admhc_init(struct admhcd *ahcd);
73 static void admhc_stop(struct usb_hcd *hcd);
74
75 #include "adm5120-dbg.c"
76 #include "adm5120-mem.c"
77 #include "adm5120-pm.c"
78 #include "adm5120-hub.c"
79 #include "adm5120-q.c"
80
81 /*-------------------------------------------------------------------------*/
82
83 /*
84 * queue up an urb for anything except the root hub
85 */
86 static int admhc_urb_enqueue(struct usb_hcd *hcd, struct usb_host_endpoint *ep,
87 struct urb *urb, gfp_t mem_flags)
88 {
89 struct admhcd *ahcd = hcd_to_admhcd(hcd);
90 struct ed *ed;
91 struct urb_priv *urb_priv;
92 unsigned int pipe = urb->pipe;
93 int td_cnt = 0;
94 unsigned long flags;
95 int ret = 0;
96
97 #ifdef ADMHC_VERBOSE_DEBUG
98 spin_lock_irqsave(&ahcd->lock, flags);
99 urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe));
100 spin_unlock_irqrestore(&ahcd->lock, flags);
101 #endif
102
103 /* every endpoint has an ed, locate and maybe (re)initialize it */
104 ed = ed_get(ahcd, ep, urb->dev, pipe, urb->interval);
105 if (!ed)
106 return -ENOMEM;
107
108 /* for the private part of the URB we need the number of TDs */
109 switch (ed->type) {
110 case PIPE_CONTROL:
111 if (urb->transfer_buffer_length > TD_DATALEN_MAX)
112 /* td_submit_urb() doesn't yet handle these */
113 return -EMSGSIZE;
114
115 /* 1 TD for setup, 1 for ACK, plus ... */
116 td_cnt = 2;
117 /* FALLTHROUGH */
118 case PIPE_BULK:
119 /* one TD for every 4096 Bytes (can be upto 8K) */
120 td_cnt += urb->transfer_buffer_length / TD_DATALEN_MAX;
121 /* ... and for any remaining bytes ... */
122 if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
123 td_cnt++;
124 /* ... and maybe a zero length packet to wrap it up */
125 if (td_cnt == 0)
126 td_cnt++;
127 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
128 && (urb->transfer_buffer_length
129 % usb_maxpacket(urb->dev, pipe,
130 usb_pipeout (pipe))) == 0)
131 td_cnt++;
132 break;
133 case PIPE_INTERRUPT:
134 /*
135 * for Interrupt IN/OUT transactions, each ED contains
136 * only 1 TD.
137 * TODO: check transfer_buffer_length?
138 */
139 td_cnt = 1;
140 break;
141 case PIPE_ISOCHRONOUS:
142 /* number of packets from URB */
143 td_cnt = urb->number_of_packets;
144 break;
145 }
146
147 urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
148 if (!urb_priv)
149 return -ENOMEM;
150
151 urb_priv->ed = ed;
152
153 spin_lock_irqsave(&ahcd->lock, flags);
154 /* don't submit to a dead HC */
155 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
156 ret = -ENODEV;
157 goto fail;
158 }
159 if (!HC_IS_RUNNING(hcd->state)) {
160 ret = -ENODEV;
161 goto fail;
162 }
163
164 /* in case of unlink-during-submit */
165 spin_lock(&urb->lock);
166 if (urb->status != -EINPROGRESS) {
167 spin_unlock(&urb->lock);
168 urb->hcpriv = urb_priv;
169 finish_urb(ahcd, urb);
170 ret = 0;
171 goto fail;
172 }
173
174 /* schedule the ed if needed */
175 if (ed->state == ED_IDLE) {
176 ret = ed_schedule(ahcd, ed);
177 if (ret < 0)
178 goto fail0;
179
180 if (ed->type == PIPE_ISOCHRONOUS) {
181 u16 frame = admhc_frame_no(ahcd);
182
183 /* delay a few frames before the first TD */
184 frame += max_t (u16, 8, ed->interval);
185 frame &= ~(ed->interval - 1);
186 frame |= ed->branch;
187 urb->start_frame = frame;
188
189 /* yes, only URB_ISO_ASAP is supported, and
190 * urb->start_frame is never used as input.
191 */
192 }
193 } else if (ed->type == PIPE_ISOCHRONOUS)
194 urb->start_frame = ed->last_iso + ed->interval;
195
196 /* fill the TDs and link them to the ed; and
197 * enable that part of the schedule, if needed
198 * and update count of queued periodic urbs
199 */
200 urb->hcpriv = urb_priv;
201 td_submit_urb(ahcd, urb);
202
203 #ifdef ADMHC_VERBOSE_DEBUG
204 admhc_dump_ed(ahcd, "admhc_urb_enqueue", urb_priv->ed, 1);
205 #endif
206
207 fail0:
208 spin_unlock(&urb->lock);
209 fail:
210 if (ret)
211 urb_priv_free(ahcd, urb_priv);
212
213 spin_unlock_irqrestore(&ahcd->lock, flags);
214 return ret;
215 }
216
217 /*
218 * decouple the URB from the HC queues (TDs, urb_priv); it's
219 * already marked using urb->status. reporting is always done
220 * asynchronously, and we might be dealing with an urb that's
221 * partially transferred, or an ED with other urbs being unlinked.
222 */
223 static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
224 {
225 struct admhcd *ahcd = hcd_to_admhcd(hcd);
226 unsigned long flags;
227
228 spin_lock_irqsave(&ahcd->lock, flags);
229
230 #ifdef ADMHC_VERBOSE_DEBUG
231 urb_print(ahcd, urb, "DEQUEUE", 1);
232 #endif
233
234 if (HC_IS_RUNNING(hcd->state)) {
235 struct urb_priv *urb_priv;
236
237 /* Unless an IRQ completed the unlink while it was being
238 * handed to us, flag it for unlink and giveback, and force
239 * some upcoming INTR_SF to call finish_unlinks()
240 */
241 urb_priv = urb->hcpriv;
242 if (urb_priv) {
243 if (urb_priv->ed->state == ED_OPER)
244 start_ed_unlink(ahcd, urb_priv->ed);
245 }
246 } else {
247 /*
248 * with HC dead, we won't respect hc queue pointers
249 * any more ... just clean up every urb's memory.
250 */
251 if (urb->hcpriv)
252 finish_urb(ahcd, urb);
253 }
254 spin_unlock_irqrestore(&ahcd->lock, flags);
255
256 return 0;
257 }
258
259 /*-------------------------------------------------------------------------*/
260
261 /* frees config/altsetting state for endpoints,
262 * including ED memory, dummy TD, and bulk/intr data toggle
263 */
264
265 static void admhc_endpoint_disable(struct usb_hcd *hcd,
266 struct usb_host_endpoint *ep)
267 {
268 struct admhcd *ahcd = hcd_to_admhcd(hcd);
269 unsigned long flags;
270 struct ed *ed = ep->hcpriv;
271 unsigned limit = 1000;
272
273 /* ASSERT: any requests/urbs are being unlinked */
274 /* ASSERT: nobody can be submitting urbs for this any more */
275
276 if (!ed)
277 return;
278
279 #ifdef ADMHC_VERBOSE_DEBUG
280 spin_lock_irqsave(&ahcd->lock, flags);
281 admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
282 spin_unlock_irqrestore(&ahcd->lock, flags);
283 #endif
284
285 rescan:
286 spin_lock_irqsave(&ahcd->lock, flags);
287
288 if (!HC_IS_RUNNING(hcd->state)) {
289 sanitize:
290 ed->state = ED_IDLE;
291 finish_unlinks(ahcd, 0);
292 }
293
294 switch (ed->state) {
295 case ED_UNLINK: /* wait for hw to finish? */
296 /* major IRQ delivery trouble loses INTR_SOFI too... */
297 if (limit-- == 0) {
298 admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
299 goto sanitize;
300 }
301 spin_unlock_irqrestore(&ahcd->lock, flags);
302 schedule_timeout_uninterruptible(1);
303 goto rescan;
304 case ED_IDLE: /* fully unlinked */
305 if (list_empty(&ed->td_list)) {
306 td_free (ahcd, ed->dummy);
307 ed_free (ahcd, ed);
308 break;
309 }
310 /* else FALL THROUGH */
311 default:
312 /* caller was supposed to have unlinked any requests;
313 * that's not our job. can't recover; must leak ed.
314 */
315 admhc_err(ahcd, "leak ed %p (#%02x) state %d%s\n",
316 ed, ep->desc.bEndpointAddress, ed->state,
317 list_empty(&ed->td_list) ? "" : " (has tds)");
318 td_free(ahcd, ed->dummy);
319 break;
320 }
321
322 ep->hcpriv = NULL;
323
324 spin_unlock_irqrestore(&ahcd->lock, flags);
325 return;
326 }
327
328 static int admhc_get_frame_number(struct usb_hcd *hcd)
329 {
330 struct admhcd *ahcd = hcd_to_admhcd(hcd);
331
332 return admhc_frame_no(ahcd);
333 }
334
335 static void admhc_usb_reset(struct admhcd *ahcd)
336 {
337 #if 0
338 ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
339 ahcd->hc_control &= OHCI_CTRL_RWC;
340 admhc_writel(ahcd, ahcd->hc_control, &ahcd->regs->control);
341 #else
342 /* FIXME */
343 ahcd->host_control = ADMHC_BUSS_RESET;
344 admhc_writel(ahcd, ahcd->host_control ,&ahcd->regs->host_control);
345 #endif
346 }
347
348 /* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
349 * other cases where the next software may expect clean state from the
350 * "firmware". this is bus-neutral, unlike shutdown() methods.
351 */
352 static void
353 admhc_shutdown(struct usb_hcd *hcd)
354 {
355 struct admhcd *ahcd;
356
357 ahcd = hcd_to_admhcd(hcd);
358 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
359 admhc_dma_disable(ahcd);
360 admhc_usb_reset(ahcd);
361 /* flush the writes */
362 admhc_writel_flush(ahcd);
363 }
364
365 /*-------------------------------------------------------------------------*
366 * HC functions
367 *-------------------------------------------------------------------------*/
368
369 static void admhc_eds_cleanup(struct admhcd *ahcd)
370 {
371 if (ahcd->ed_tails[PIPE_INTERRUPT]) {
372 ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
373 ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
374 }
375
376 if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
377 ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
378 ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
379 }
380
381 if (ahcd->ed_tails[PIPE_CONTROL]) {
382 ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
383 ahcd->ed_tails[PIPE_CONTROL] = NULL;
384 }
385
386 if (ahcd->ed_tails[PIPE_BULK]) {
387 ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
388 ahcd->ed_tails[PIPE_BULK] = NULL;
389 }
390
391 ahcd->ed_head = NULL;
392 }
393
394 #define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
395
396 static int admhc_eds_init(struct admhcd *ahcd)
397 {
398 struct ed *ed;
399
400 ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
401 if (!ed)
402 goto err;
403
404 ahcd->ed_tails[PIPE_INTERRUPT] = ed;
405
406 ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
407 if (!ed)
408 goto err;
409
410 ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
411 ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
412 ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
413 ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
414
415 ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
416 if (!ed)
417 goto err;
418
419 ahcd->ed_tails[PIPE_CONTROL] = ed;
420 ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
421 ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
422 ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
423
424 ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
425 if (!ed)
426 goto err;
427
428 ahcd->ed_tails[PIPE_BULK] = ed;
429 ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
430 ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
431 ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
432
433 ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
434
435 #ifdef ADMHC_VERBOSE_DEBUG
436 admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
437 admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
438 admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
439 admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
440 #endif
441
442 return 0;
443
444 err:
445 admhc_eds_cleanup(ahcd);
446 return -ENOMEM;
447 }
448
449 /* init memory, and kick BIOS/SMM off */
450
451 static int admhc_init(struct admhcd *ahcd)
452 {
453 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
454 int ret;
455
456 admhc_disable(ahcd);
457 ahcd->regs = hcd->regs;
458
459 /* Disable HC interrupts */
460 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
461
462 /* Read the number of ports unless overridden */
463 if (ahcd->num_ports == 0)
464 ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP;
465
466 ret = admhc_mem_init(ahcd);
467 if (ret)
468 goto err;
469
470 /* init dummy endpoints */
471 ret = admhc_eds_init(ahcd);
472 if (ret)
473 goto err;
474
475 create_debug_files(ahcd);
476
477 return 0;
478
479 err:
480 admhc_stop(hcd);
481 return ret;
482 }
483
484 /*-------------------------------------------------------------------------*/
485
486 /* Start an OHCI controller, set the BUS operational
487 * resets USB and controller
488 * enable interrupts
489 */
490 static int admhc_run(struct admhcd *ahcd)
491 {
492 u32 temp;
493 int first = ahcd->fminterval == 0;
494 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
495
496 admhc_disable(ahcd);
497
498 /* boot firmware should have set this up (5.1.1.3.1) */
499 if (first) {
500 temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
501 ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
502 if (ahcd->fminterval != FI)
503 admhc_dbg(ahcd, "fminterval delta %d\n",
504 ahcd->fminterval - FI);
505 ahcd->fminterval |=
506 (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
507 /* also: power/overcurrent flags in rhdesc */
508 }
509
510 #if 0 /* TODO: not applicable */
511 /* Reset USB nearly "by the book". RemoteWakeupConnected was
512 * saved if boot firmware (BIOS/SMM/...) told us it's connected,
513 * or if bus glue did the same (e.g. for PCI add-in cards with
514 * PCI PM support).
515 */
516 if ((ahcd->hc_control & OHCI_CTRL_RWC) != 0
517 && !device_may_wakeup(hcd->self.controller))
518 device_init_wakeup(hcd->self.controller, 1);
519 #endif
520
521 switch (ahcd->host_control & ADMHC_HC_BUSS) {
522 case ADMHC_BUSS_OPER:
523 temp = 0;
524 break;
525 case ADMHC_BUSS_SUSPEND:
526 /* FALLTHROUGH ? */
527 case ADMHC_BUSS_RESUME:
528 ahcd->host_control = ADMHC_BUSS_RESUME;
529 temp = 10 /* msec wait */;
530 break;
531 /* case ADMHC_BUSS_RESET: */
532 default:
533 ahcd->host_control = ADMHC_BUSS_RESET;
534 temp = 50 /* msec wait */;
535 break;
536 }
537 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
538
539 /* flush the writes */
540 admhc_writel_flush(ahcd);
541
542 msleep(temp);
543 temp = admhc_read_rhdesc(ahcd);
544 if (!(temp & ADMHC_RH_NPS)) {
545 /* power down each port */
546 for (temp = 0; temp < ahcd->num_ports; temp++)
547 admhc_write_portstatus(ahcd, temp, ADMHC_PS_CPP);
548 }
549 /* flush those writes */
550 admhc_writel_flush(ahcd);
551
552 /* 2msec timelimit here means no irqs/preempt */
553 spin_lock_irq(&ahcd->lock);
554
555 admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
556 temp = 30; /* ... allow extra time */
557 while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
558 if (--temp == 0) {
559 spin_unlock_irq(&ahcd->lock);
560 admhc_err(ahcd, "USB HC reset timed out!\n");
561 return -1;
562 }
563 udelay(1);
564 }
565
566 /* enable HOST mode, before access any host specific register */
567 admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
568
569 /* Tell the controller where the descriptor list is */
570 admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
571
572 periodic_reinit(ahcd);
573
574 /* use rhsc irqs after khubd is fully initialized */
575 hcd->poll_rh = 1;
576 hcd->uses_new_polling = 1;
577
578 #if 0
579 /* wake on ConnectStatusChange, matching external hubs */
580 admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
581 #else
582 /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
583 #endif
584
585 /* Choose the interrupts we care about now, others later on demand */
586 admhc_intr_ack(ahcd, ~0);
587 admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
588
589 admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
590
591 /* flush those writes */
592 admhc_writel_flush(ahcd);
593
594 /* start controller operations */
595 ahcd->host_control = ADMHC_BUSS_OPER;
596 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
597
598 temp = 20;
599 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
600 & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
601 if (--temp == 0) {
602 spin_unlock_irq(&ahcd->lock);
603 admhc_err(ahcd, "unable to setup operational mode!\n");
604 return -1;
605 }
606 mdelay(1);
607 }
608
609 hcd->state = HC_STATE_RUNNING;
610
611 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
612
613 #if 0
614 /* FIXME: enabling DMA is always failed here for an unknown reason */
615 admhc_dma_enable(ahcd);
616
617 temp = 200;
618 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
619 & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) {
620 if (--temp == 0) {
621 spin_unlock_irq(&ahcd->lock);
622 admhc_err(ahcd, "unable to enable DMA!\n");
623 admhc_dump(ahcd, 1);
624 return -1;
625 }
626 mdelay(1);
627 }
628
629 #endif
630
631 spin_unlock_irq(&ahcd->lock);
632
633 mdelay(ADMHC_POTPGT);
634
635 return 0;
636 }
637
638 /*-------------------------------------------------------------------------*/
639
640 /* an interrupt happens */
641
642 static irqreturn_t admhc_irq(struct usb_hcd *hcd)
643 {
644 struct admhcd *ahcd = hcd_to_admhcd(hcd);
645 struct admhcd_regs __iomem *regs = ahcd->regs;
646 u32 ints;
647
648 ints = admhc_readl(ahcd, &regs->int_status);
649 if ((ints & ADMHC_INTR_INTA) == 0) {
650 /* no unmasked interrupt status is set */
651 return IRQ_NONE;
652 }
653
654 ints &= admhc_readl(ahcd, &regs->int_enable);
655
656 if (ints & ADMHC_INTR_FATI) {
657 /* e.g. due to PCI Master/Target Abort */
658 admhc_disable(ahcd);
659 admhc_err(ahcd, "Fatal Error, controller disabled\n");
660 admhc_dump(ahcd, 1);
661 admhc_usb_reset(ahcd);
662 }
663
664 if (ints & ADMHC_INTR_BABI) {
665 admhc_intr_disable(ahcd, ADMHC_INTR_BABI);
666 admhc_intr_ack(ahcd, ADMHC_INTR_BABI);
667 admhc_err(ahcd, "Babble Detected\n");
668 }
669
670 if (ints & ADMHC_INTR_INSM) {
671 admhc_vdbg(ahcd, "Root Hub Status Change\n");
672 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
673 admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
674
675 /* NOTE: Vendors didn't always make the same implementation
676 * choices for RHSC. Many followed the spec; RHSC triggers
677 * on an edge, like setting and maybe clearing a port status
678 * change bit. With others it's level-triggered, active
679 * until khubd clears all the port status change bits. We'll
680 * always disable it here and rely on polling until khubd
681 * re-enables it.
682 */
683 admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
684 usb_hcd_poll_rh_status(hcd);
685 } else if (ints & ADMHC_INTR_RESI) {
686 /* For connect and disconnect events, we expect the controller
687 * to turn on RHSC along with RD. But for remote wakeup events
688 * this might not happen.
689 */
690 admhc_vdbg(ahcd, "Resume Detect\n");
691 admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
692 hcd->poll_rh = 1;
693 if (ahcd->autostop) {
694 spin_lock(&ahcd->lock);
695 admhc_rh_resume(ahcd);
696 spin_unlock(&ahcd->lock);
697 } else
698 usb_hcd_resume_root_hub(hcd);
699 }
700
701 if (ints & ADMHC_INTR_TDC) {
702 admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
703 admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
704 if (HC_IS_RUNNING(hcd->state))
705 admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
706 spin_lock(&ahcd->lock);
707 admhc_td_complete(ahcd);
708 spin_unlock(&ahcd->lock);
709 if (HC_IS_RUNNING(hcd->state))
710 admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
711 }
712
713 if (ints & ADMHC_INTR_SO) {
714 /* could track INTR_SO to reduce available PCI/... bandwidth */
715 admhc_vdbg(ahcd, "Schedule Overrun\n");
716 }
717
718 #if 1
719 spin_lock(&ahcd->lock);
720 if (ahcd->ed_rm_list)
721 finish_unlinks(ahcd, admhc_frame_no(ahcd));
722
723 if ((ints & ADMHC_INTR_SOFI) != 0 && !ahcd->ed_rm_list
724 && HC_IS_RUNNING(hcd->state))
725 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
726 spin_unlock(&ahcd->lock);
727 #else
728 if (ints & ADMHC_INTR_SOFI) {
729 admhc_vdbg(ahcd, "Start Of Frame\n");
730 spin_lock(&ahcd->lock);
731
732 /* handle any pending ED removes */
733 finish_unlinks(ahcd, admhc_frameno(ahcd));
734
735 /* leaving INTR_SOFI enabled when there's still unlinking
736 * to be done in the (next frame).
737 */
738 if ((ahcd->ed_rm_list == NULL) ||
739 HC_IS_RUNNING(hcd->state) == 0)
740 /*
741 * disable INTR_SOFI if there are no unlinking to be
742 * done (in the next frame)
743 */
744 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
745
746 spin_unlock(&ahcd->lock);
747 }
748 #endif
749
750 if (HC_IS_RUNNING(hcd->state)) {
751 admhc_intr_ack(ahcd, ints);
752 admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
753 admhc_writel_flush(ahcd);
754 }
755
756 return IRQ_HANDLED;
757 }
758
759 /*-------------------------------------------------------------------------*/
760
761 static void admhc_stop(struct usb_hcd *hcd)
762 {
763 struct admhcd *ahcd = hcd_to_admhcd(hcd);
764
765 admhc_dump(ahcd, 1);
766
767 flush_scheduled_work();
768
769 admhc_usb_reset(ahcd);
770 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
771
772 free_irq(hcd->irq, hcd);
773 hcd->irq = -1;
774
775 remove_debug_files(ahcd);
776 admhc_eds_cleanup(ahcd);
777 admhc_mem_cleanup(ahcd);
778 }
779
780 /*-------------------------------------------------------------------------*/
781
782 #ifdef CONFIG_MIPS_ADM5120
783 #include "adm5120-drv.c"
784 #define PLATFORM_DRIVER usb_hcd_adm5120_driver
785 #endif
786
787 #if !defined(PLATFORM_DRIVER)
788 #error "missing bus glue for admhc-hcd"
789 #endif
790
791 #define DRIVER_INFO DRIVER_DESC " version " DRIVER_VERSION
792
793 static int __init admhc_hcd_mod_init(void)
794 {
795 int ret = 0;
796
797 if (usb_disabled())
798 return -ENODEV;
799
800 pr_info("%s: " DRIVER_INFO "\n", hcd_name);
801 pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
802 sizeof (struct ed), sizeof (struct td));
803
804 #ifdef PLATFORM_DRIVER
805 ret = platform_driver_register(&PLATFORM_DRIVER);
806 if (ret < 0)
807 goto error_platform;
808 #endif
809
810 return ret;
811
812 #ifdef PLATFORM_DRIVER
813 platform_driver_unregister(&PLATFORM_DRIVER);
814 error_platform:
815 #endif
816 return ret;
817 }
818 module_init(admhc_hcd_mod_init);
819
820 static void __exit admhc_hcd_mod_exit(void)
821 {
822 platform_driver_unregister(&PLATFORM_DRIVER);
823 }
824 module_exit(admhc_hcd_mod_exit);
825
826 MODULE_AUTHOR(DRIVER_AUTHOR);
827 MODULE_DESCRIPTION(DRIVER_INFO);
828 MODULE_VERSION(DRIVER_VERSION);
829 MODULE_LICENSE("GPL");