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[adm5120] checkin a new, experimental USB driver
[openwrt/svn-archive/archive.git] / target / linux / adm5120 / files / drivers / usb / host / adm5120-q.c
1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * This file is licenced under the GPL.
8 */
9
10 #include <linux/irq.h>
11
12 /*-------------------------------------------------------------------------*/
13
14 /*
15 * URB goes back to driver, and isn't reissued.
16 * It's completely gone from HC data structures.
17 * PRECONDITION: ahcd lock held, irqs blocked.
18 */
19 static void
20 finish_urb(struct admhcd *ahcd, struct urb *urb)
21 __releases(ahcd->lock)
22 __acquires(ahcd->lock)
23 {
24 urb_priv_free(ahcd, urb->hcpriv);
25 urb->hcpriv = NULL;
26
27 spin_lock(&urb->lock);
28 if (likely(urb->status == -EINPROGRESS))
29 urb->status = 0;
30
31 /* report short control reads right even though the data TD always
32 * has TD_R set. (much simpler, but creates the 1-td limit.)
33 */
34 if (unlikely(urb->transfer_flags & URB_SHORT_NOT_OK)
35 && unlikely(usb_pipecontrol(urb->pipe))
36 && urb->actual_length < urb->transfer_buffer_length
37 && usb_pipein(urb->pipe)
38 && urb->status == 0) {
39 urb->status = -EREMOTEIO;
40 #ifdef ADMHC_VERBOSE_DEBUG
41 urb_print(urb, "SHORT", usb_pipeout (urb->pipe));
42 #endif
43 }
44 spin_unlock(&urb->lock);
45
46 switch (usb_pipetype(urb->pipe)) {
47 case PIPE_ISOCHRONOUS:
48 admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs--;
49 break;
50 case PIPE_INTERRUPT:
51 admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs--;
52 break;
53 }
54
55 #ifdef ADMHC_VERBOSE_DEBUG
56 urb_print(urb, "RET", usb_pipeout (urb->pipe));
57 #endif
58
59 /* urb->complete() can reenter this HCD */
60 spin_unlock(&ahcd->lock);
61 usb_hcd_giveback_urb(admhcd_to_hcd(ahcd), urb);
62 spin_lock(&ahcd->lock);
63 }
64
65
66 /*-------------------------------------------------------------------------*
67 * ED handling functions
68 *-------------------------------------------------------------------------*/
69
70 #if 0 /* FIXME */
71 /* search for the right schedule branch to use for a periodic ed.
72 * does some load balancing; returns the branch, or negative errno.
73 */
74 static int balance(struct admhcd *ahcd, int interval, int load)
75 {
76 int i, branch = -ENOSPC;
77
78 /* iso periods can be huge; iso tds specify frame numbers */
79 if (interval > NUM_INTS)
80 interval = NUM_INTS;
81
82 /* search for the least loaded schedule branch of that period
83 * that has enough bandwidth left unreserved.
84 */
85 for (i = 0; i < interval ; i++) {
86 if (branch < 0 || ahcd->load [branch] > ahcd->load [i]) {
87 int j;
88
89 /* usb 1.1 says 90% of one frame */
90 for (j = i; j < NUM_INTS; j += interval) {
91 if ((ahcd->load [j] + load) > 900)
92 break;
93 }
94 if (j < NUM_INTS)
95 continue;
96 branch = i;
97 }
98 }
99 return branch;
100 }
101 #endif
102
103 /*-------------------------------------------------------------------------*/
104
105 #if 0 /* FIXME */
106 /* both iso and interrupt requests have periods; this routine puts them
107 * into the schedule tree in the apppropriate place. most iso devices use
108 * 1msec periods, but that's not required.
109 */
110 static void periodic_link (struct admhcd *ahcd, struct ed *ed)
111 {
112 unsigned i;
113
114 admhc_vdbg (ahcd, "link %sed %p branch %d [%dus.], interval %d\n",
115 (ed->hwINFO & cpu_to_hc32 (ahcd, ED_ISO)) ? "iso " : "",
116 ed, ed->branch, ed->load, ed->interval);
117
118 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
119 struct ed **prev = &ahcd->periodic [i];
120 __hc32 *prev_p = &ahcd->hcca->int_table [i];
121 struct ed *here = *prev;
122
123 /* sorting each branch by period (slow before fast)
124 * lets us share the faster parts of the tree.
125 * (plus maybe: put interrupt eds before iso)
126 */
127 while (here && ed != here) {
128 if (ed->interval > here->interval)
129 break;
130 prev = &here->ed_next;
131 prev_p = &here->hwNextED;
132 here = *prev;
133 }
134 if (ed != here) {
135 ed->ed_next = here;
136 if (here)
137 ed->hwNextED = *prev_p;
138 wmb ();
139 *prev = ed;
140 *prev_p = cpu_to_hc32(ahcd, ed->dma);
141 wmb();
142 }
143 ahcd->load [i] += ed->load;
144 }
145 admhcd_to_hcd(ahcd)->self.bandwidth_allocated += ed->load / ed->interval;
146 }
147 #endif
148
149 /* link an ed into the HC chain */
150
151 static int ed_schedule(struct admhcd *ahcd, struct ed *ed)
152 {
153 struct ed *old_tail;
154
155 if (admhcd_to_hcd(ahcd)->state == HC_STATE_QUIESCING)
156 return -EAGAIN;
157
158 ed->state = ED_OPER;
159
160 old_tail = ahcd->ed_tails[ed->type];
161
162 ed->ed_next = old_tail->ed_next;
163 if (ed->ed_next) {
164 ed->ed_next->ed_prev = ed;
165 ed->hwNextED = cpu_to_hc32(ahcd, ed->ed_next->dma);
166 }
167 ed->ed_prev = old_tail;
168
169 old_tail->ed_next = ed;
170 old_tail->hwNextED = cpu_to_hc32(ahcd, ed->dma);
171
172 ahcd->ed_tails[ed->type] = ed;
173
174 admhc_dma_enable(ahcd);
175
176 return 0;
177 }
178
179 /*-------------------------------------------------------------------------*/
180
181 #if 0 /* FIXME */
182 /* scan the periodic table to find and unlink this ED */
183 static void periodic_unlink (struct admhcd *ahcd, struct ed *ed)
184 {
185 int i;
186
187 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
188 struct ed *temp;
189 struct ed **prev = &ahcd->periodic [i];
190 __hc32 *prev_p = &ahcd->hcca->int_table [i];
191
192 while (*prev && (temp = *prev) != ed) {
193 prev_p = &temp->hwNextED;
194 prev = &temp->ed_next;
195 }
196 if (*prev) {
197 *prev_p = ed->hwNextED;
198 *prev = ed->ed_next;
199 }
200 ahcd->load [i] -= ed->load;
201 }
202
203 admhcd_to_hcd(ahcd)->self.bandwidth_allocated -= ed->load / ed->interval;
204 admhc_vdbg (ahcd, "unlink %sed %p branch %d [%dus.], interval %d\n",
205 (ed->hwINFO & cpu_to_hc32 (ahcd, ED_ISO)) ? "iso " : "",
206 ed, ed->branch, ed->load, ed->interval);
207 }
208 #endif
209
210 /* unlink an ed from the HC chain.
211 * just the link to the ed is unlinked.
212 * the link from the ed still points to another operational ed or 0
213 * so the HC can eventually finish the processing of the unlinked ed
214 * (assuming it already started that, which needn't be true).
215 *
216 * ED_UNLINK is a transient state: the HC may still see this ED, but soon
217 * it won't. ED_SKIP means the HC will finish its current transaction,
218 * but won't start anything new. The TD queue may still grow; device
219 * drivers don't know about this HCD-internal state.
220 *
221 * When the HC can't see the ED, something changes ED_UNLINK to one of:
222 *
223 * - ED_OPER: when there's any request queued, the ED gets rescheduled
224 * immediately. HC should be working on them.
225 *
226 * - ED_IDLE: when there's no TD queue. there's no reason for the HC
227 * to care about this ED; safe to disable the endpoint.
228 *
229 * When finish_unlinks() runs later, after SOF interrupt, it will often
230 * complete one or more URB unlinks before making that state change.
231 */
232 static void ed_deschedule(struct admhcd *ahcd, struct ed *ed)
233 {
234 ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
235 wmb();
236 ed->state = ED_UNLINK;
237
238 /* remove this ED from the HC list */
239 ed->ed_prev->hwNextED = ed->hwNextED;
240
241 /* and remove it from our list also */
242 ed->ed_prev->ed_next = ed->ed_next;
243
244 if (ed->ed_next)
245 ed->ed_next->ed_prev = ed->ed_prev;
246
247 if (ahcd->ed_tails[ed->type] == ed)
248 ahcd->ed_tails[ed->type] = ed->ed_prev;
249 }
250
251 /*-------------------------------------------------------------------------*/
252
253 static struct ed *ed_create(struct admhcd *ahcd, unsigned int type, u32 info)
254 {
255 struct ed *ed;
256 struct td *td;
257
258 ed = ed_alloc(ahcd, GFP_ATOMIC);
259 if (!ed)
260 goto err;
261
262 /* dummy td; end of td list for this ed */
263 td = td_alloc(ahcd, GFP_ATOMIC);
264 if (!td)
265 goto err_free_ed;
266
267 switch (type) {
268 case PIPE_INTERRUPT:
269 info |= ED_INT;
270 break;
271 case PIPE_ISOCHRONOUS:
272 info |= ED_ISO;
273 break;
274 }
275
276 ed->dummy = td;
277 ed->state = ED_IDLE;
278 ed->type = type;
279
280 ed->hwINFO = cpu_to_hc32(ahcd, info);
281 ed->hwTailP = cpu_to_hc32(ahcd, td->td_dma);
282 ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
283
284 return ed;
285
286 err_free_ed:
287 ed_free(ahcd, ed);
288 err:
289 return NULL;
290 }
291
292 /* get and maybe (re)init an endpoint. init _should_ be done only as part
293 * of enumeration, usb_set_configuration() or usb_set_interface().
294 */
295 static struct ed *ed_get(struct admhcd *ahcd, struct usb_host_endpoint *ep,
296 struct usb_device *udev, unsigned int pipe, int interval)
297 {
298 struct ed *ed;
299 unsigned long flags;
300
301 spin_lock_irqsave(&ahcd->lock, flags);
302 ed = ep->hcpriv;
303 if (!ed) {
304 u32 info;
305
306 /* FIXME: usbcore changes dev->devnum before SET_ADDRESS
307 * suceeds ... otherwise we wouldn't need "pipe".
308 */
309 info = usb_pipedevice(pipe);
310 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << ED_EN_SHIFT;
311 info |= le16_to_cpu(ep->desc.wMaxPacketSize) << ED_MPS_SHIFT;
312 if (udev->speed == USB_SPEED_FULL)
313 info |= ED_SPEED_FULL;
314
315 ed = ed_create(ahcd, usb_pipetype(pipe), info);
316 if (ed)
317 ep->hcpriv = ed;
318 }
319 spin_unlock_irqrestore(&ahcd->lock, flags);
320
321 return ed;
322 }
323
324 /*-------------------------------------------------------------------------*/
325
326 /* request unlinking of an endpoint from an operational HC.
327 * put the ep on the rm_list
328 * real work is done at the next start frame (SOFI) hardware interrupt
329 * caller guarantees HCD is running, so hardware access is safe,
330 * and that ed->state is ED_OPER
331 */
332 static void start_ed_unlink(struct admhcd *ahcd, struct ed *ed)
333 {
334 ed->hwINFO |= cpu_to_hc32 (ahcd, ED_DEQUEUE);
335 ed_deschedule(ahcd, ed);
336
337 /* add this ED into the remove list */
338 ed->ed_rm_next = ahcd->ed_rm_list;
339 ahcd->ed_rm_list = ed;
340
341 /* enable SOF interrupt */
342 admhc_intr_ack(ahcd, ADMHC_INTR_SOFI);
343 admhc_intr_enable(ahcd, ADMHC_INTR_SOFI);
344 /* flush those writes */
345 admhc_writel_flush(ahcd);
346
347 /* SOF interrupt might get delayed; record the frame counter value that
348 * indicates when the HC isn't looking at it, so concurrent unlinks
349 * behave. frame_no wraps every 2^16 msec, and changes right before
350 * SOF is triggered.
351 */
352 ed->tick = admhc_frame_no(ahcd) + 1;
353 }
354
355 /*-------------------------------------------------------------------------*
356 * TD handling functions
357 *-------------------------------------------------------------------------*/
358
359 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
360
361 static void
362 td_fill(struct admhcd *ahcd, u32 info, dma_addr_t data, int len,
363 struct urb *urb, int index)
364 {
365 struct td *td, *td_pt;
366 struct urb_priv *urb_priv = urb->hcpriv;
367 int hash;
368 u32 cbl = 0;
369
370 #if 1
371 if (index == (urb_priv->td_cnt - 1) &&
372 ((urb->transfer_flags & URB_NO_INTERRUPT) == 0))
373 cbl |= TD_IE;
374 #else
375 if (index == (urb_priv->td_cnt - 1))
376 cbl |= TD_IE;
377 #endif
378
379 /* use this td as the next dummy */
380 td_pt = urb_priv->td[index];
381
382 /* fill the old dummy TD */
383 td = urb_priv->td[index] = urb_priv->ed->dummy;
384 urb_priv->ed->dummy = td_pt;
385
386 td->ed = urb_priv->ed;
387 td->next_dl_td = NULL;
388 td->index = index;
389 td->urb = urb;
390 td->data_dma = data;
391 if (!len)
392 data = 0;
393
394 if (data)
395 cbl |= (len & TD_BL_MASK);
396
397 info |= TD_OWN;
398
399 /* setup hardware specific fields */
400 td->hwINFO = cpu_to_hc32(ahcd, info);
401 td->hwDBP = cpu_to_hc32(ahcd, data);
402 td->hwCBL = cpu_to_hc32(ahcd, cbl);
403 td->hwNextTD = cpu_to_hc32(ahcd, td_pt->td_dma);
404
405 /* append to queue */
406 list_add_tail(&td->td_list, &td->ed->td_list);
407
408 /* hash it for later reverse mapping */
409 hash = TD_HASH_FUNC(td->td_dma);
410 td->td_hash = ahcd->td_hash[hash];
411 ahcd->td_hash[hash] = td;
412
413 /* HC might read the TD (or cachelines) right away ... */
414 wmb();
415 td->ed->hwTailP = td->hwNextTD;
416 }
417
418 /*-------------------------------------------------------------------------*/
419
420 /* Prepare all TDs of a transfer, and queue them onto the ED.
421 * Caller guarantees HC is active.
422 * Usually the ED is already on the schedule, so TDs might be
423 * processed as soon as they're queued.
424 */
425 static void td_submit_urb(struct admhcd *ahcd, struct urb *urb)
426 {
427 struct urb_priv *urb_priv = urb->hcpriv;
428 dma_addr_t data;
429 int data_len = urb->transfer_buffer_length;
430 int cnt = 0;
431 u32 info = 0;
432 int is_out = usb_pipeout(urb->pipe);
433 int periodic = 0;
434 u32 toggle = 0;
435 struct td *td;
436
437 /* OHCI handles the bulk/interrupt data toggles itself. We just
438 * use the device toggle bits for resetting, and rely on the fact
439 * that resetting toggle is meaningless if the endpoint is active.
440 */
441
442 if (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), is_out)) {
443 toggle = TD_T_CARRY;
444 } else {
445 toggle = TD_T_DATA0;
446 usb_settoggle(urb->dev, usb_pipeendpoint (urb->pipe),
447 is_out, 1);
448 }
449
450 urb_priv->td_idx = 0;
451 list_add(&urb_priv->pending, &ahcd->pending);
452
453 if (data_len)
454 data = urb->transfer_dma;
455 else
456 data = 0;
457
458 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
459 * using TD_CC_GET, as well as by seeing them on the done list.
460 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
461 */
462 switch (urb_priv->ed->type) {
463 case PIPE_INTERRUPT:
464 info = is_out
465 ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
466 : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
467
468 /* setup service interval and starting frame number */
469 info |= (urb->start_frame & TD_FN_MASK);
470 info |= (urb->interval & TD_ISI_MASK) << TD_ISI_SHIFT;
471
472 td_fill(ahcd, info, data, data_len, urb, cnt);
473 cnt++;
474
475 admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs++;
476 break;
477
478 case PIPE_BULK:
479 info = is_out
480 ? TD_SCC_NOTACCESSED | TD_DP_OUT
481 : TD_SCC_NOTACCESSED | TD_DP_IN;
482
483 /* TDs _could_ transfer up to 8K each */
484 while (data_len > TD_DATALEN_MAX) {
485 td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
486 data, TD_DATALEN_MAX, urb, cnt);
487 data += TD_DATALEN_MAX;
488 data_len -= TD_DATALEN_MAX;
489 cnt++;
490 }
491
492 td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle), data,
493 data_len, urb, cnt);
494 cnt++;
495
496 if ((urb->transfer_flags & URB_ZERO_PACKET)
497 && (cnt < urb_priv->td_cnt)) {
498 td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
499 0, 0, urb, cnt);
500 cnt++;
501 }
502 break;
503
504 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
505 * any DATA phase works normally, and the STATUS ack is special.
506 */
507 case PIPE_CONTROL:
508 /* fill a TD for the setup */
509 info = TD_SCC_NOTACCESSED | TD_DP_SETUP | TD_T_DATA0;
510 td_fill(ahcd, info, urb->setup_dma, 8, urb, cnt++);
511
512 if (data_len > 0) {
513 /* fill a TD for the data */
514 info = TD_SCC_NOTACCESSED | TD_T_DATA1;
515 info |= is_out ? TD_DP_OUT : TD_DP_IN;
516 /* NOTE: mishandles transfers >8K, some >4K */
517 td_fill(ahcd, info, data, data_len, urb, cnt++);
518 }
519
520 /* fill a TD for the ACK */
521 info = (is_out || data_len == 0)
522 ? TD_SCC_NOTACCESSED | TD_DP_IN | TD_T_DATA1
523 : TD_SCC_NOTACCESSED | TD_DP_OUT | TD_T_DATA1;
524 td_fill(ahcd, info, data, 0, urb, cnt++);
525
526 break;
527
528 /* ISO has no retransmit, so no toggle;
529 * Each TD could handle multiple consecutive frames (interval 1);
530 * we could often reduce the number of TDs here.
531 */
532 case PIPE_ISOCHRONOUS:
533 info = TD_SCC_NOTACCESSED;
534 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
535 int frame = urb->start_frame;
536
537 frame += cnt * urb->interval;
538 frame &= TD_FN_MASK;
539 td_fill(ahcd, info | frame,
540 data + urb->iso_frame_desc[cnt].offset,
541 urb->iso_frame_desc[cnt].length, urb, cnt);
542 }
543 admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs++;
544 break;
545 }
546
547 if (urb_priv->td_cnt != cnt)
548 admhc_err(ahcd, "bad number of tds created for urb %p\n", urb);
549 }
550
551 /*-------------------------------------------------------------------------*
552 * Done List handling functions
553 *-------------------------------------------------------------------------*/
554
555 /* calculate transfer length/status and update the urb
556 * PRECONDITION: irqsafe (only for urb->status locking)
557 */
558 static void td_done(struct admhcd *ahcd, struct urb *urb, struct td *td)
559 {
560 u32 info = hc32_to_cpup(ahcd, &td->hwINFO);
561 int type = usb_pipetype(urb->pipe);
562 int cc = TD_CC_NOERROR;
563
564 /* ISO ... drivers see per-TD length/status */
565 if (type == PIPE_ISOCHRONOUS) {
566 #if 0
567 /* TODO */
568 int dlen = 0;
569
570 /* NOTE: assumes FC in tdINFO == 0, and that
571 * only the first of 0..MAXPSW psws is used.
572 */
573
574 cc = TD_CC_GET(td);
575 if (tdINFO & TD_CC) /* hc didn't touch? */
576 return;
577
578 if (usb_pipeout (urb->pipe))
579 dlen = urb->iso_frame_desc [td->index].length;
580 else {
581 /* short reads are always OK for ISO */
582 if (cc == TD_DATAUNDERRUN)
583 cc = TD_CC_NOERROR;
584 dlen = tdPSW & 0x3ff;
585 }
586 urb->actual_length += dlen;
587 urb->iso_frame_desc [td->index].actual_length = dlen;
588 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
589
590 if (cc != TD_CC_NOERROR)
591 admhc_vdbg (ahcd,
592 "urb %p iso td %p (%d) len %d cc %d\n",
593 urb, td, 1 + td->index, dlen, cc);
594 #endif
595 /* BULK, INT, CONTROL ... drivers see aggregate length/status,
596 * except that "setup" bytes aren't counted and "short" transfers
597 * might not be reported as errors.
598 */
599 } else {
600 u32 bl = TD_BL_GET(hc32_to_cpup(ahcd, &td->hwCBL));
601 u32 tdDBP = hc32_to_cpup(ahcd, &td->hwDBP);
602
603 cc = TD_CC_GET(info);
604
605 /* update packet status if needed (short is normally ok) */
606 if (cc == TD_CC_DATAUNDERRUN
607 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
608 cc = TD_CC_NOERROR;
609
610 if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0) {
611 admhc_dump_ed(ahcd, "CC ERROR", td->ed, 1);
612 spin_lock(&urb->lock);
613 if (urb->status == -EINPROGRESS)
614 urb->status = cc_to_error[cc];
615 spin_unlock(&urb->lock);
616 }
617
618 /* count all non-empty packets except control SETUP packet */
619 if ((type != PIPE_CONTROL || td->index != 0) && tdDBP != 0) {
620 urb->actual_length += tdDBP - td->data_dma + bl;
621 }
622
623 if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
624 admhc_vdbg(ahcd,
625 "urb %p td %p (%d) cc %d, len=%d/%d\n",
626 urb, td, td->index, cc,
627 urb->actual_length,
628 urb->transfer_buffer_length);
629 }
630
631 list_del(&td->td_list);
632
633 }
634
635 /*-------------------------------------------------------------------------*/
636
637 static inline struct td *
638 ed_halted(struct admhcd *ahcd, struct td *td, int cc, struct td *rev)
639 {
640 struct urb *urb = td->urb;
641 struct ed *ed = td->ed;
642 struct list_head *tmp = td->td_list.next;
643 __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ahcd, ED_C);
644
645 admhc_dump_ed(ahcd, "ed halted", td->ed, 1);
646 /* clear ed halt; this is the td that caused it, but keep it inactive
647 * until its urb->complete() has a chance to clean up.
648 */
649 ed->hwINFO |= cpu_to_hc32 (ahcd, ED_SKIP);
650 wmb ();
651 ed->hwHeadP &= ~cpu_to_hc32 (ahcd, ED_H);
652
653 /* put any later tds from this urb onto the donelist, after 'td',
654 * order won't matter here: no errors, and nothing was transferred.
655 * also patch the ed so it looks as if those tds completed normally.
656 */
657 while (tmp != &ed->td_list) {
658 struct td *next;
659 __hc32 info;
660
661 next = list_entry(tmp, struct td, td_list);
662 tmp = next->td_list.next;
663
664 if (next->urb != urb)
665 break;
666
667 /* NOTE: if multi-td control DATA segments get supported,
668 * this urb had one of them, this td wasn't the last td
669 * in that segment (TD_R clear), this ed halted because
670 * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
671 * then we need to leave the control STATUS packet queued
672 * and clear ED_SKIP.
673 */
674 info = next->hwINFO;
675 #if 0 /* FIXME */
676 info |= cpu_to_hc32 (ahcd, TD_DONE);
677 info &= ~cpu_to_hc32 (ahcd, TD_CC);
678 #endif
679 next->hwINFO = info;
680
681 next->next_dl_td = rev;
682 rev = next;
683
684 ed->hwHeadP = next->hwNextTD | toggle;
685 }
686
687 /* help for troubleshooting: report anything that
688 * looks odd ... that doesn't include protocol stalls
689 * (or maybe some other things)
690 */
691 switch (cc) {
692 case TD_CC_DATAUNDERRUN:
693 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
694 break;
695 /* fallthrough */
696 case TD_CC_STALL:
697 if (usb_pipecontrol (urb->pipe))
698 break;
699 /* fallthrough */
700 default:
701 admhc_dbg (ahcd,
702 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
703 urb, urb->dev->devpath,
704 usb_pipeendpoint (urb->pipe),
705 usb_pipein (urb->pipe) ? "in" : "out",
706 hc32_to_cpu(ahcd, td->hwINFO),
707 cc, cc_to_error [cc]);
708 }
709
710 return rev;
711 }
712
713 /*-------------------------------------------------------------------------*/
714
715 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
716 static void
717 finish_unlinks(struct admhcd *ahcd, u16 tick)
718 {
719 struct ed *ed, **last;
720
721 rescan_all:
722 for (last = &ahcd->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
723 struct list_head *entry, *tmp;
724 int completed, modified;
725 __hc32 *prev;
726
727 /* only take off EDs that the HC isn't using, accounting for
728 * frame counter wraps and EDs with partially retired TDs
729 */
730 if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))) {
731 if (tick_before (tick, ed->tick)) {
732 skip_ed:
733 last = &ed->ed_rm_next;
734 continue;
735 }
736
737 if (!list_empty (&ed->td_list)) {
738 struct td *td;
739 u32 head;
740
741 td = list_entry(ed->td_list.next, struct td,
742 td_list);
743 head = hc32_to_cpu(ahcd, ed->hwHeadP) &
744 TD_MASK;
745
746 /* INTR_WDH may need to clean up first */
747 if (td->td_dma != head)
748 goto skip_ed;
749 }
750 }
751
752 /* reentrancy: if we drop the schedule lock, someone might
753 * have modified this list. normally it's just prepending
754 * entries (which we'd ignore), but paranoia won't hurt.
755 */
756 *last = ed->ed_rm_next;
757 ed->ed_rm_next = NULL;
758 modified = 0;
759
760 /* unlink urbs as requested, but rescan the list after
761 * we call a completion since it might have unlinked
762 * another (earlier) urb
763 *
764 * When we get here, the HC doesn't see this ed. But it
765 * must not be rescheduled until all completed URBs have
766 * been given back to the driver.
767 */
768 rescan_this:
769 completed = 0;
770 prev = &ed->hwHeadP;
771 list_for_each_safe (entry, tmp, &ed->td_list) {
772 struct td *td;
773 struct urb *urb;
774 struct urb_priv *urb_priv;
775 __hc32 savebits;
776
777 td = list_entry(entry, struct td, td_list);
778 urb = td->urb;
779 urb_priv = td->urb->hcpriv;
780
781 if (urb->status == -EINPROGRESS) {
782 prev = &td->hwNextTD;
783 continue;
784 }
785
786 if ((urb_priv) == NULL)
787 continue;
788
789 /* patch pointer hc uses */
790 savebits = *prev & ~cpu_to_hc32(ahcd, TD_MASK);
791 *prev = td->hwNextTD | savebits;
792
793 /* HC may have partly processed this TD */
794 urb_print(urb, "PARTIAL",1);
795 td_done(ahcd, urb, td);
796 urb_priv->td_idx++;
797
798 /* if URB is done, clean up */
799 if (urb_priv->td_idx == urb_priv->td_cnt) {
800 modified = completed = 1;
801 finish_urb(ahcd, urb);
802 }
803 }
804 if (completed && !list_empty (&ed->td_list))
805 goto rescan_this;
806
807 /* ED's now officially unlinked, hc doesn't see */
808 ed->state = ED_IDLE;
809 ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
810 ed->hwNextED = 0;
811 wmb ();
812 ed->hwINFO &= ~cpu_to_hc32 (ahcd, ED_SKIP | ED_DEQUEUE);
813
814 /* but if there's work queued, reschedule */
815 if (!list_empty (&ed->td_list)) {
816 if (HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))
817 ed_schedule(ahcd, ed);
818 }
819
820 if (modified)
821 goto rescan_all;
822 }
823 }
824
825 /*-------------------------------------------------------------------------*/
826
827 /*
828 * Process normal completions (error or success) and clean the schedules.
829 *
830 * This is the main path for handing urbs back to drivers. The only other
831 * path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of
832 * scanning the (re-reversed) donelist as this does.
833 */
834
835 static void ed_update(struct admhcd *ahcd, struct ed *ed)
836 {
837 struct list_head *entry,*tmp;
838
839 admhc_dump_ed(ahcd, "ed update", ed, 1);
840
841 list_for_each_safe(entry, tmp, &ed->td_list) {
842 struct td *td = list_entry(entry, struct td, td_list);
843 struct urb *urb = td->urb;
844 struct urb_priv *urb_priv = urb->hcpriv;
845
846 if (hc32_to_cpup(ahcd, &td->hwINFO) & TD_OWN)
847 break;
848
849 /* update URB's length and status from TD */
850 td_done(ahcd, urb, td);
851 urb_priv->td_idx++;
852
853 /* If all this urb's TDs are done, call complete() */
854 if (urb_priv->td_idx == urb_priv->td_cnt)
855 finish_urb(ahcd, urb);
856
857 /* clean schedule: unlink EDs that are no longer busy */
858 if (list_empty(&ed->td_list)) {
859 if (ed->state == ED_OPER)
860 start_ed_unlink(ahcd, ed);
861
862 /* ... reenabling halted EDs only after fault cleanup */
863 } else if ((ed->hwINFO & cpu_to_hc32 (ahcd,
864 ED_SKIP | ED_DEQUEUE))
865 == cpu_to_hc32 (ahcd, ED_SKIP)) {
866 td = list_entry(ed->td_list.next, struct td, td_list);
867 #if 0
868 if (!(td->hwINFO & cpu_to_hc32 (ahcd, TD_DONE))) {
869 ed->hwINFO &= ~cpu_to_hc32 (ahcd, ED_SKIP);
870 /* ... hc may need waking-up */
871 switch (ed->type) {
872 case PIPE_CONTROL:
873 admhc_writel (ahcd, OHCI_CLF,
874 &ahcd->regs->cmdstatus);
875 break;
876 case PIPE_BULK:
877 admhc_writel (ahcd, OHCI_BLF,
878 &ahcd->regs->cmdstatus);
879 break;
880 }
881 }
882 #else
883 if ((td->hwINFO & cpu_to_hc32(ahcd, TD_OWN)))
884 ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
885 #endif
886 }
887
888 }
889 }
890
891 static void ed_halt(struct admhcd *ahcd, struct ed *ed)
892 {
893 admhc_dump_ed(ahcd, "ed_halt", ed, 1);
894 }
895
896 /* there are some tds completed; called in_irq(), with HCD locked */
897 static void admhc_td_complete(struct admhcd *ahcd)
898 {
899 struct ed *ed;
900
901 for (ed = ahcd->ed_head; ed; ed = ed->ed_next) {
902 if (ed->state != ED_OPER)
903 continue;
904
905 if (hc32_to_cpup(ahcd, &ed->hwINFO) & ED_SKIP)
906 continue;
907
908 if (hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) {
909 ed_halt(ahcd, ed);
910 continue;
911 }
912
913 ed_update(ahcd, ed);
914 }
915 }
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