target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_nand.h

   1 /*
   2  *  ADM5120 NAND interface definitions
   3  *
   4  *  This header file defines the hardware registers of the ADM5120 SoC
   5  *  built-in NAND interface.
   6  *
   7  *  Copyright (C) 2007 OpenWrt.org
   8  *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
   9  *
  10  *  NAND interface routines was based on a driver for Linux 2.6.19+ which
  11  *  was derived from the driver for Linux 2.4.xx published by Mikrotik for
  12  *  their RouterBoard 1xx and 5xx series boards.
  13  *    Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk>
  14  *    Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
  15  *    The original Mikrotik code seems not to have a license.
  16  *
  17  *  This program is free software; you can redistribute it and/or
  18  *  modify it under the terms of the GNU General Public License
  19  *  as published by the Free Software Foundation; either version 2
  20  *  of the License, or (at your option) any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful,
  23  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  *  GNU General Public License for more details.
  26  *
  27  *  You should have received a copy of the GNU General Public License
  28  *  along with this program; if not, write to the
  29  *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  30  *  Boston, MA  02110-1301, USA.
  31  *
  32  */
  33
  34 #ifndef _ADM5120_NAND_H_
  35 #define _ADM5120_NAND_H_
  36
  37 #include <linux/types.h>
  38 #include <linux/io.h>
  39
  40 #include <adm5120_defs.h>
  41 #include <adm5120_switch.h>
  42
  43 /* NAND control registers */
  44 #define NAND_REG_DATA           0x0 /* data register */
  45 #define NAND_REG_SET_CEn        0x1 /* CE# low */
  46 #define NAND_REG_CLR_CEn        0x2 /* CE# high */
  47 #define NAND_REG_CLR_CLE        0x3 /* CLE low */
  48 #define NAND_REG_SET_CLE        0x4 /* CLE high */
  49 #define NAND_REG_CLR_ALE        0x5 /* ALE low */
  50 #define NAND_REG_SET_ALE        0x6 /* ALE high */
  51 #define NAND_REG_SET_SPn        0x7 /* SP# low (use spare area) */
  52 #define NAND_REG_CLR_SPn        0x8 /* SP# high (do not use spare area) */
  53 #define NAND_REG_SET_WPn        0x9 /* WP# low */
  54 #define NAND_REG_CLR_WPn        0xA /* WP# high */
  55 #define NAND_REG_STATUS         0xB /* Status register */
  56
  57 #define ADM5120_NAND_STATUS_READY       0x80
  58
  59 #define NAND_READ_REG(r) \
  60         readb((void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
  61 #define NAND_WRITE_REG(r, v) \
  62         writeb((v),(void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
  63
  64 /*-------------------------------------------------------------------------*/
  65
  66 static inline void adm5120_nand_enable(void)
  67 {
  68         SW_WRITE_REG(BW_CNTL1, BW_CNTL1_NAND_ENABLE);
  69         SW_WRITE_REG(BOOT_DONE, 1);
  70 }
  71
  72 static inline void adm5120_nand_set_wpn(unsigned int set)
  73 {
  74         NAND_WRITE_REG((set) ? NAND_REG_SET_WPn : NAND_REG_CLR_WPn, 1);
  75 }
  76
  77 static inline void adm5120_nand_set_spn(unsigned int set)
  78 {
  79         NAND_WRITE_REG((set) ? NAND_REG_SET_SPn : NAND_REG_CLR_SPn, 1);
  80 }
  81
  82 static inline void adm5120_nand_set_cle(unsigned int set)
  83 {
  84         NAND_WRITE_REG((set) ? NAND_REG_SET_CLE : NAND_REG_CLR_CLE, 1);
  85 }
  86
  87 static inline void adm5120_nand_set_ale(unsigned int set)
  88 {
  89         NAND_WRITE_REG((set) ? NAND_REG_SET_ALE : NAND_REG_CLR_ALE, 1);
  90 }
  91
  92 static inline void adm5120_nand_set_cen(unsigned int set)
  93 {
  94         NAND_WRITE_REG((set) ? NAND_REG_SET_CEn : NAND_REG_CLR_CEn, 1);
  95 }
  96
  97 static inline u8 adm5120_nand_get_status(void)
  98 {
  99         return NAND_READ_REG(NAND_REG_STATUS);
 100 }
 101
 102 #endif /* _ADM5120_NAND_H_ */