target/linux/amazon/files/arch/mips/amazon/pci.c

   1 /*
   2  *  Carsten Langgaard, carstenl@mips.com
   3  *  Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
   4  *  Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  */
  19
  20 /* FIXME: convert nasty volatile register derefs to readl/writel calls */
  21
  22 #include <linux/types.h>
  23 #include <linux/pci.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <asm/io.h>
  29 #include <asm/paccess.h>
  30 #include <asm/amazon/irq.h>
  31 #include <asm/amazon/amazon.h>
  32
  33 #define AMAZON_PCI_REG32( addr )                  (*(volatile u32 *)(addr))
  34 #ifndef AMAZON_PCI_MEM_BASE
  35 #define AMAZON_PCI_MEM_BASE    0xb2000000
  36 #endif
  37 #define AMAZON_PCI_MEM_SIZE    0x00400000
  38 #define AMAZON_PCI_IO_BASE     0xb2400000
  39 #define AMAZON_PCI_IO_SIZE     0x00002000
  40
  41 #define AMAZON_PCI_CFG_BUSNUM_SHF 16
  42 #define AMAZON_PCI_CFG_DEVNUM_SHF 11
  43 #define AMAZON_PCI_CFG_FUNNUM_SHF 8
  44
  45 #define PCI_ACCESS_READ  0
  46 #define PCI_ACCESS_WRITE 1
  47
  48 static inline u32 amazon_r32(u32 addr)
  49 {
  50         u32 *ptr = (u32 *) addr;
  51         return __raw_readl(ptr);
  52 }
  53
  54 static inline void amazon_w32(u32 addr, u32 val)
  55 {
  56         u32 *ptr = (u32 *) addr;
  57         __raw_writel(val, ptr);
  58 }
  59
  60
  61 static struct resource pci_io_resource = {
  62         .name = "io pci IO space",
  63 #if 0
  64         .start = AMAZON_PCI_IO_BASE,
  65         .end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1,
  66 #endif
  67         .start = 0,
  68         .end = AMAZON_PCI_IO_SIZE - 1,
  69         .flags = IORESOURCE_IO
  70 };
  71
  72 static struct resource pci_mem_resource = {
  73         .name = "ext pci memory space",
  74         .start = AMAZON_PCI_MEM_BASE,
  75         .end = AMAZON_PCI_MEM_BASE + AMAZON_PCI_MEM_SIZE - 1,
  76         .flags = IORESOURCE_MEM
  77 };
  78
  79 static inline u32 amazon_pci_swap(u32 val)
  80 {
  81 #ifdef CONFIG_AMAZON_PCI_HW_SWAP
  82         return swab32(val);
  83 #else
  84         return val;
  85 #endif
  86 }
  87
  88 static int amazon_pci_config_access(unsigned char access_type,
  89         struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
  90 {
  91         unsigned long flags;
  92         u32 pci_addr;
  93         u32 val;
  94         int ret;
  95
  96         /* Amazon support slot from 0 to 15 */
  97         /* devfn 0 & 0x20 is itself */
  98         if ((bus->number != 0) || (devfn == 0) || (devfn == 0x20))
  99                 return 1;
 100
 101         pci_addr=AMAZON_PCI_CFG_BASE |
 102                 bus->number << AMAZON_PCI_CFG_BUSNUM_SHF |
 103                 devfn << AMAZON_PCI_CFG_FUNNUM_SHF |
 104                 (where & ~0x3);
 105
 106         local_irq_save(flags);
 107         if (access_type == PCI_ACCESS_WRITE) {
 108                 val = amazon_pci_swap(*data);
 109                 ret = put_dbe(val, (u32 *)pci_addr);
 110         } else {
 111                 ret = get_dbe(val, (u32 *)pci_addr);
 112                 *data = amazon_pci_swap(val);
 113         }
 114
 115         amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
 116         amazon_w32(STATUS_COMMAND_ADDR, amazon_r32(STATUS_COMMAND_ADDR));
 117         amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
 118         local_irq_restore(flags);
 119
 120         return ret;
 121 }
 122
 123
 124 static int amazon_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
 125 {
 126         u32 data = 0;
 127
 128         if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 129                 return PCIBIOS_DEVICE_NOT_FOUND;
 130
 131         if (size == 1)
 132                 *val = (data >> ((where & 3) << 3)) & 0xff;
 133         else if (size == 2)
 134                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 135         else
 136                 *val = data;
 137
 138         return PCIBIOS_SUCCESSFUL;
 139 }
 140
 141
 142 static int amazon_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 143 {
 144         u32 data = 0;
 145
 146         if (size == 4)
 147         {
 148                 data = val;
 149         } else {
 150                 if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 151                         return PCIBIOS_DEVICE_NOT_FOUND;
 152
 153                 if (size == 1)
 154                         data = (data & ~(0xff << ((where & 3) << 3))) |
 155                                 (val << ((where & 3) << 3));
 156                 else if (size == 2)
 157                         data = (data & ~(0xffff << ((where & 3) << 3))) |
 158                                 (val << ((where & 3) << 3));
 159         }
 160
 161         if (amazon_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 162                 return PCIBIOS_DEVICE_NOT_FOUND;
 163
 164         return PCIBIOS_SUCCESSFUL;
 165 }
 166
 167 static struct pci_ops amazon_pci_ops = {
 168         amazon_pci_read,
 169         amazon_pci_write
 170 };
 171
 172 static struct pci_controller amazon_pci_controller = {
 173         .pci_ops = &amazon_pci_ops,
 174         .mem_resource = &pci_mem_resource,
 175         .io_resource = &pci_io_resource
 176 };
 177
 178 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 179 {
 180         switch (slot) {
 181                 case 13:
 182                         /* IDSEL = AD29 --> USB Host Controller */
 183                         return INT_NUM_IM2_IRL15;
 184                 case 14:
 185                         /* IDSEL = AD30 --> mini PCI connector */
 186                         return INT_NUM_IM2_IRL14;
 187                 default:
 188                         printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
 189                         return 0;
 190         }
 191 }
 192
 193 int pcibios_plat_dev_init(struct pci_dev *dev)
 194 {
 195         switch(dev->irq) {
 196                 case INT_NUM_IM2_IRL15:
 197                         /*
 198                          * IDSEL = AD29 --> USB Host Controller
 199                          * PCI_INTA/B/C--GPIO Port0.2--EXIN3
 200                          * IN/ALT0:1 ALT1:0
 201                          * PULL UP
 202                          */
 203                         (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffb;
 204                         (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 4;
 205                         (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffb;
 206                         (*AMAZON_GPIO_P0_PUDSEL) =  (*AMAZON_GPIO_P0_PUDSEL) | 4;
 207                         (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 4;
 208                         //External Interrupt Node
 209                         (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x6000; /* Low Level triggered */
 210                         (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x8;
 211                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 212                         break;
 213                 case INT_NUM_IM2_IRL14:
 214                         /*
 215                          * IDSEL = AD30 --> mini PCI connector
 216                          * PCI_INTA--GPIO Port0.1--EXIN2
 217                          * IN/ALT0:1 ALT1:0
 218                          * PULL UP
 219                          */
 220                         (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffd;
 221                         (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 2;
 222                         (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffd;
 223                         (*AMAZON_GPIO_P0_PUDSEL) =  (*AMAZON_GPIO_P0_PUDSEL) | 2;
 224                         (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 2;
 225                         //External Interrupt Node
 226                         (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x600;
 227                         (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x4;
 228                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 229                         break;
 230                 default:
 231                         return 1;
 232         }
 233         return 0;
 234 }
 235
 236 int __init amazon_pci_init(void)
 237 {
 238         u32 temp_buffer;
 239
 240 #ifdef CONFIG_AMAZON_PCI_HW_SWAP
 241         AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28);
 242         wmb();
 243 #endif
 244
 245         AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1<<ARB_CTRL_bit);
 246         amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
 247
 248         AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) = AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) | (1<<BUS_MASTER_ENABLE_BIT) |(1<<MEM_SPACE_ENABLE_BIT);
 249
 250         temp_buffer = AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR);
 251         temp_buffer = temp_buffer | (1<< INTERNAL_ARB_ENABLE_BIT);
 252         temp_buffer = temp_buffer & ~(3<< PCI_MASTER0_REQ_MASK_2BITS);
 253         temp_buffer = temp_buffer & ~(3<< PCI_MASTER0_GNT_MASK_2BITS);
 254
 255         /* flash */
 256         temp_buffer = temp_buffer & ~(3<< PCI_MASTER1_REQ_MASK_2BITS);
 257         temp_buffer = temp_buffer & ~(3<< PCI_MASTER1_GNT_MASK_2BITS);
 258
 259         /* external master */
 260         temp_buffer = temp_buffer & ~(3<< PCI_MASTER2_REQ_MASK_2BITS);
 261         temp_buffer = temp_buffer & ~(3<< PCI_MASTER2_GNT_MASK_2BITS);
 262
 263         AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR) = temp_buffer;
 264         wmb();
 265
 266         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_0) = 0xb2000000;
 267         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_1) = 0xb2100000;
 268         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_2) = 0xb2200000;
 269         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_3) = 0xb2300000;
 270         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_4) = 0xb2400000;
 271         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_5) = 0xb2500000;
 272         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_6) = 0xb2600000;
 273         AMAZON_PCI_REG32(FPI_ADDRESS_MAP_7) = 0xb2700000;
 274
 275         AMAZON_PCI_REG32(BAR11_MASK) = 0x0f000008;
 276         AMAZON_PCI_REG32(PCI_ADDRESS_MAP_11) = 0x0;
 277         AMAZON_PCI_REG32(BAR1_ADDR) = 0x0;
 278         amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
 279         //use 8 dw burse length
 280         AMAZON_PCI_REG32(FPI_BURST_LENGTH) = 0x303;
 281
 282         amazon_pci_controller.io_map_base = (unsigned long)ioremap(AMAZON_PCI_IO_BASE, AMAZON_PCI_IO_SIZE);
 283         register_pci_controller(&amazon_pci_controller);
 284         return 0;
 285 }
 286 arch_initcall(amazon_pci_init);