target/linux/ar7-2.6/files/arch/mips/ar7/clock.c

   1 /*
   2  * $Id$
   3  *
   4  * Copyright (C) 2007 OpenWrt.org
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/types.h>
  23 #include <linux/module.h>
  24 #include <linux/delay.h>
  25 #include <asm/addrspace.h>
  26 #include <asm/io.h>
  27 #include <asm/ar7/ar7.h>
  28
  29 #define BOOT_PLL_SOURCE_MASK 0x3
  30 #define CPU_PLL_SOURCE_SHIFT 16
  31 #define BUS_PLL_SOURCE_SHIFT 14
  32 #define USB_PLL_SOURCE_SHIFT 18
  33 #define DSP_PLL_SOURCE_SHIFT 22
  34 #define BOOT_PLL_SOURCE_AFE 0
  35 #define BOOT_PLL_SOURCE_BUS 0
  36 #define BOOT_PLL_SOURCE_REF 1
  37 #define BOOT_PLL_SOURCE_XTAL 2
  38 #define BOOT_PLL_SOURCE_CPU 3
  39 #define BOOT_PLL_BYPASS 0x00000020
  40 #define BOOT_PLL_ASYNC_MODE 0x02000000
  41 #define BOOT_PLL_2TO1_MODE 0x00008000
  42
  43 #define TNETD7200_CLOCK_ID_CPU 0
  44 #define TNETD7200_CLOCK_ID_DSP 1
  45 #define TNETD7200_CLOCK_ID_USB 2
  46
  47 #define TNETD7200_DEF_CPU_CLK 211000000
  48 #define TNETD7200_DEF_DSP_CLK 125000000
  49 #define TNETD7200_DEF_USB_CLK 48000000
  50
  51 struct tnetd7300_clock {
  52         volatile u32 ctrl;
  53 #define PREDIV_MASK 0x001f0000
  54 #define PREDIV_SHIFT 16
  55 #define POSTDIV_MASK 0x0000001f
  56         u32 unused1[3];
  57         volatile u32 pll;
  58 #define MUL_MASK 0x0000f000
  59 #define MUL_SHIFT 12
  60 #define PLL_MODE_MASK 0x00000001
  61 #define PLL_NDIV 0x00000800
  62 #define PLL_DIV 0x00000002
  63 #define PLL_STATUS 0x00000001
  64         u32 unused2[3];
  65 } __attribute__ ((packed));
  66
  67 struct tnetd7300_clocks {
  68         struct tnetd7300_clock bus;
  69         struct tnetd7300_clock cpu;
  70         struct tnetd7300_clock usb;
  71         struct tnetd7300_clock dsp;
  72 } __attribute__ ((packed));
  73
  74 struct tnetd7200_clock {
  75         volatile u32 ctrl;
  76         u32 unused1[3];
  77 #define DIVISOR_ENABLE_MASK 0x00008000
  78         volatile u32 mul;
  79         volatile u32 prediv;
  80         volatile u32 postdiv;
  81         volatile u32 postdiv2;
  82         u32 unused2[6];
  83         volatile u32 cmd;
  84         volatile u32 status;
  85         volatile u32 cmden;
  86         u32 padding[15];
  87 } __attribute__ ((packed));
  88
  89 struct tnetd7200_clocks {
  90         struct tnetd7200_clock cpu;
  91         struct tnetd7200_clock dsp;
  92         struct tnetd7200_clock usb;
  93 } __attribute__ ((packed));
  94
  95 int ar7_cpu_clock = 150000000;
  96 EXPORT_SYMBOL(ar7_cpu_clock);
  97 int ar7_bus_clock = 125000000;
  98 EXPORT_SYMBOL(ar7_bus_clock);
  99 int ar7_dsp_clock = 0;
 100 EXPORT_SYMBOL(ar7_dsp_clock);
 101
 102 static int gcd(int x, int y)
 103 {
 104         if (x > y)
 105                 return (x % y) ? gcd(y, x % y) : y;
 106         return (y % x) ? gcd(x, y % x) : x;
 107 }
 108
 109 static inline int ABS(int x)
 110 {
 111         return (x >= 0) ? x : -x;
 112 }
 113
 114 static void approximate(int base, int target, int *prediv,
 115                         int *postdiv, int *mul)
 116 {
 117         int i, j, k, freq, res = target;
 118         for (i = 1; i <= 16; i++) {
 119                 for (j = 1; j <= 32; j++) {
 120                         for (k = 1; k <= 32; k++) {
 121                                 freq = ABS(base / j * i / k - target);
 122                                 if (freq < res) {
 123                                         res = freq;
 124                                         *mul = i;
 125                                         *prediv = j;
 126                                         *postdiv = k;
 127                                 }
 128                         }
 129                 }
 130         }
 131 }
 132
 133 static void calculate(int base, int target, int *prediv, int *postdiv,
 134         int *mul)
 135 {
 136         int tmp_gcd, tmp_base, tmp_freq;
 137
 138         for (*prediv = 1; *prediv <= 32; (*prediv)++) {
 139                 tmp_base = base / *prediv;
 140                 tmp_gcd = gcd(target, tmp_base);
 141                 *mul = target / tmp_gcd;
 142                 *postdiv = tmp_base / tmp_gcd;
 143                 if ((*mul < 1) || (*mul >= 16))
 144                         continue;
 145                 if ((*postdiv > 0) & (*postdiv <= 32))
 146                         break;
 147         }
 148
 149         if (base / (*prediv) * (*mul) / (*postdiv) != target) {
 150                 approximate(base, target, prediv, postdiv, mul);
 151                 tmp_freq = base / (*prediv) * (*mul) / (*postdiv);
 152                 printk(KERN_WARNING
 153                        "Adjusted requested frequency %d to %d\n",
 154                        target, tmp_freq);
 155         }
 156
 157         printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
 158                *prediv, *postdiv, *mul);
 159 }
 160
 161 static int tnetd7300_dsp_clock(void)
 162 {
 163         u32 didr1, didr2;
 164         u8 rev = ar7_chip_rev();
 165         didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
 166         didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
 167         if (didr2 & (1 << 23))
 168                 return 0;
 169         if ((rev >= 0x23) && (rev != 0x57))
 170                 return 250000000;
 171         if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
 172             > 4208000)
 173                 return 250000000;
 174         return 0;
 175 }
 176
 177 static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
 178         u32 *bootcr, u32 bus_clock)
 179 {
 180         int product;
 181         int base_clock = AR7_REF_CLOCK;
 182         u32 ctrl = clock->ctrl;
 183         u32 pll = clock->pll;
 184         int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
 185         int postdiv = (ctrl & POSTDIV_MASK) + 1;
 186         int divisor = prediv * postdiv;
 187         int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
 188
 189         switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
 190         case BOOT_PLL_SOURCE_BUS:
 191                 base_clock = bus_clock;
 192                 break;
 193         case BOOT_PLL_SOURCE_REF:
 194                 base_clock = AR7_REF_CLOCK;
 195                 break;
 196         case BOOT_PLL_SOURCE_XTAL:
 197                 base_clock = AR7_XTAL_CLOCK;
 198                 break;
 199         case BOOT_PLL_SOURCE_CPU:
 200                 base_clock = ar7_cpu_clock;
 201                 break;
 202         }
 203
 204         if (*bootcr & BOOT_PLL_BYPASS)
 205                 return base_clock / divisor;
 206
 207         if ((pll & PLL_MODE_MASK) == 0)
 208                 return (base_clock >> (mul / 16 + 1)) / divisor;
 209
 210         if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
 211                 product = (mul & 1) ?
 212                         (base_clock * mul) >> 1 :
 213                         (base_clock * (mul - 1)) >> 2;
 214                 return product / divisor;
 215         }
 216
 217         if (mul == 16)
 218                 return base_clock / divisor;
 219
 220         return base_clock * mul / divisor;
 221 }
 222
 223 static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
 224         u32 *bootcr, u32 frequency)
 225 {
 226         u32 status;
 227         int prediv, postdiv, mul;
 228         int base_clock = ar7_bus_clock;
 229
 230         switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
 231         case BOOT_PLL_SOURCE_BUS:
 232                 base_clock = ar7_bus_clock;
 233                 break;
 234         case BOOT_PLL_SOURCE_REF:
 235                 base_clock = AR7_REF_CLOCK;
 236                 break;
 237         case BOOT_PLL_SOURCE_XTAL:
 238                 base_clock = AR7_XTAL_CLOCK;
 239                 break;
 240         case BOOT_PLL_SOURCE_CPU:
 241                 base_clock = ar7_cpu_clock;
 242                 break;
 243         }
 244
 245         calculate(base_clock, frequency, &prediv, &postdiv, &mul);
 246
 247         clock->ctrl = ((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1);
 248         mdelay(1);
 249         clock->pll = 4;
 250         do {
 251                 status = clock->pll;
 252         } while (status & PLL_STATUS);
 253         clock->pll = ((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e;
 254         mdelay(75);
 255 }
 256
 257 static void __init tnetd7300_init_clocks(void)
 258 {
 259         u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
 260         struct tnetd7300_clocks *clocks = (struct tnetd7300_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x20, sizeof(struct tnetd7300_clocks));
 261
 262         ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
 263                 &clocks->bus, bootcr, AR7_AFE_CLOCK);
 264
 265         if (*bootcr & BOOT_PLL_ASYNC_MODE) {
 266                 ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
 267                         &clocks->cpu, bootcr, AR7_AFE_CLOCK);
 268         } else {
 269                 ar7_cpu_clock = ar7_bus_clock;
 270         }
 271
 272         tnetd7300_set_clock(USB_PLL_SOURCE_SHIFT, &clocks->usb,
 273                 bootcr, 48000000);
 274
 275         if (ar7_dsp_clock == 250000000)
 276                 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
 277                         bootcr, ar7_dsp_clock);
 278
 279         iounmap(clocks);
 280         iounmap(bootcr);
 281 }
 282
 283 static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
 284         u32 *bootcr, u32 bus_clock)
 285 {
 286         int divisor = ((clock->prediv & 0x1f) + 1) *
 287                 ((clock->postdiv & 0x1f) + 1);
 288
 289         if (*bootcr & BOOT_PLL_BYPASS)
 290                 return base / divisor;
 291
 292         return base * ((clock->mul & 0xf) + 1) / divisor;
 293 }
 294
 295
 296 static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
 297         int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
 298 {
 299         printk("Clocks: base = %d, frequency = %u, prediv = %d, postdiv = %d, postdiv2 = %d, mul = %d\n",
 300                 base, frequency, prediv, postdiv, postdiv2, mul);
 301
 302         clock->ctrl = 0;
 303         clock->prediv = DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F);
 304         clock->mul = ((mul - 1) & 0xF);
 305
 306         for(mul = 0; mul < 2000; mul++) /* nop */;
 307
 308         while(clock->status & 0x1) /* nop */;
 309
 310         clock->postdiv = DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F);
 311
 312         clock->cmden |= 1;
 313         clock->cmd |= 1;
 314
 315         while(clock->status & 0x1) /* nop */;
 316
 317         clock->postdiv2 = DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F);
 318
 319         clock->cmden |= 1;
 320         clock->cmd |= 1;
 321
 322         while(clock->status & 0x1) /* nop */;
 323
 324         clock->ctrl |= 1;
 325 }
 326
 327 static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
 328 {
 329         if (*bootcr & BOOT_PLL_ASYNC_MODE) {
 330                 // Async
 331                 switch (clock_id) {
 332                 case TNETD7200_CLOCK_ID_DSP:
 333                         return AR7_REF_CLOCK;
 334                 default:
 335                         return AR7_AFE_CLOCK;
 336                 }
 337         } else {
 338                 // Sync
 339                 if (*bootcr & BOOT_PLL_2TO1_MODE) {
 340                         // 2:1
 341                         switch (clock_id) {
 342                         case TNETD7200_CLOCK_ID_DSP:
 343                                 return AR7_REF_CLOCK;
 344                         default:
 345                                 return AR7_AFE_CLOCK;
 346                         }
 347                 } else {
 348                         // 1:1
 349                         return AR7_REF_CLOCK;
 350                 }
 351         }
 352 }
 353
 354
 355 static void __init tnetd7200_init_clocks(void)
 356 {
 357         u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
 358         struct tnetd7200_clocks *clocks = (struct tnetd7200_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x80, sizeof(struct tnetd7200_clocks));
 359         int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
 360         int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
 361         int usb_base, usb_mul, usb_prediv, usb_postdiv;
 362
 363 /*
 364         Log from Fritz!Box 7170 Annex B:
 365
 366         CPU revision is: 00018448
 367         Clocks: Async mode
 368         Clocks: Setting DSP clock
 369         Clocks: prediv: 1, postdiv: 1, mul: 5
 370         Clocks: base = 25000000, frequency = 125000000, prediv = 1, postdiv = 2, postdiv2 = 1, mul = 10
 371         Clocks: Setting CPU clock
 372         Adjusted requested frequency 211000000 to 211968000
 373         Clocks: prediv: 1, postdiv: 1, mul: 6
 374         Clocks: base = 35328000, frequency = 211968000, prediv = 1, postdiv = 1, postdiv2 = -1, mul = 6
 375         Clocks: Setting USB clock
 376         Adjusted requested frequency 48000000 to 48076920
 377         Clocks: prediv: 13, postdiv: 1, mul: 5
 378         Clocks: base = 125000000, frequency = 48000000, prediv = 13, postdiv = 1, postdiv2 = -1, mul = 5
 379
 380         DSL didn't work if you didn't set the postdiv 2:1 postdiv2 combination, driver hung on startup.
 381         Haven't tested this on a synchronous board, neither do i know what to do with ar7_dsp_clock
 382 */
 383
 384         cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
 385         dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
 386
 387         if (*bootcr & BOOT_PLL_ASYNC_MODE) {
 388                 printk("Clocks: Async mode\n");
 389
 390                 printk("Clocks: Setting DSP clock\n");
 391                 calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
 392                 ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
 393                 tnetd7200_set_clock(dsp_base, &clocks->dsp,
 394                         dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
 395                         ar7_bus_clock);
 396
 397                 printk("Clocks: Setting CPU clock\n");
 398                 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, &cpu_postdiv, &cpu_mul);
 399                 ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
 400                 tnetd7200_set_clock(cpu_base, &clocks->cpu,
 401                         cpu_prediv, cpu_postdiv, -1, cpu_mul,
 402                         ar7_cpu_clock);
 403
 404         } else {
 405                 if (*bootcr & BOOT_PLL_2TO1_MODE) {
 406                         printk("Clocks: Sync 2:1 mode\n");
 407
 408                         printk("Clocks: Setting CPU clock\n");
 409                         calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, &cpu_postdiv, &cpu_mul);
 410                         ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
 411                         tnetd7200_set_clock(cpu_base, &clocks->cpu,
 412                                 cpu_prediv, cpu_postdiv, -1, cpu_mul,
 413                                 ar7_cpu_clock);
 414
 415                         printk("Clocks: Setting DSP clock\n");
 416                         calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
 417                         ar7_bus_clock = ar7_cpu_clock / 2;
 418                         tnetd7200_set_clock(dsp_base, &clocks->dsp,
 419                                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
 420                                 ar7_bus_clock);
 421                 } else {
 422                         printk("Clocks: Sync 1:1 mode\n");
 423
 424                         printk("Clocks: Setting DSP clock\n");
 425                         calculate(dsp_base, TNETD7200_DEF_CPU_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
 426                         ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
 427                         tnetd7200_set_clock(dsp_base, &clocks->dsp,
 428                                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
 429                                 ar7_bus_clock);
 430
 431                         ar7_cpu_clock = ar7_bus_clock;
 432                 }
 433         }
 434
 435         printk("Clocks: Setting USB clock\n");
 436         usb_base = ar7_bus_clock;
 437         calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv, &usb_postdiv, &usb_mul);
 438         tnetd7200_set_clock(usb_base, &clocks->usb,
 439                 usb_prediv, usb_postdiv, -1, usb_mul,
 440                 TNETD7200_DEF_USB_CLK);
 441
 442         #warning FIXME: ????! Hrmm
 443         ar7_dsp_clock = ar7_cpu_clock;
 444
 445         iounmap(clocks);
 446         iounmap(bootcr);
 447 }
 448
 449 void __init ar7_init_clocks(void)
 450 {
 451         switch (ar7_chip_id()) {
 452         case AR7_CHIP_7100:
 453 #warning FIXME: Check if the new 7200 clock init works for 7100
 454                 tnetd7200_init_clocks();
 455                 break;
 456         case AR7_CHIP_7200:
 457                 tnetd7200_init_clocks();
 458                 break;
 459         case AR7_CHIP_7300:
 460                 ar7_dsp_clock = tnetd7300_dsp_clock();
 461                 tnetd7300_init_clocks();
 462                 break;
 463         default:
 464                 break;
 465         }
 466 }