target/linux/ar7-2.6/files/arch/mips/ar7/irq.c

   1 /*
   2  * $Id$
   3  *
   4  * Copyright (C) 2006, 2007 OpenWrt.org
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/ioport.h>
  24
  25 #include <asm/irq.h>
  26 #include <asm/irq_cpu.h>
  27 #include <asm/mipsregs.h>
  28 #include <asm/ar7/ar7.h>
  29
  30 #define EXCEPT_OFFSET 0x80
  31 #define PACE_OFFSET   0xA0
  32 #define CHNLS_OFFSET  0x200
  33
  34 #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
  35 #define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
  36 #define SEC_SR_OFFSET  (SEC_REG_OFFSET(0))      /* 0x80 */
  37 #define CR_OFFSET(irq)  (REG_OFFSET(irq, 1))    /* 0x10 */
  38 #define SEC_CR_OFFSET  (SEC_REG_OFFSET(1))      /* 0x88 */
  39 #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2))    /* 0x20 */
  40 #define SEC_ESR_OFFSET  (SEC_REG_OFFSET(2))     /* 0x90 */
  41 #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3))    /* 0x30 */
  42 #define SEC_ECR_OFFSET  (SEC_REG_OFFSET(3))     /* 0x98 */
  43 #define PIR_OFFSET      (0x40)
  44 #define MSR_OFFSET      (0x44)
  45 #define PM_OFFSET(irq)  (REG_OFFSET(irq, 5))    /* 0x50 */
  46 #define TM_OFFSET(irq)  (REG_OFFSET(irq, 6))    /* 0x60 */
  47
  48 #define REG(addr) (*(volatile u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
  49
  50 #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
  51
  52 static void ar7_unmask_irq(unsigned int irq_nr);
  53 static void ar7_mask_irq(unsigned int irq_nr);
  54 static void ar7_unmask_secondary_irq(unsigned int irq_nr);
  55 static void ar7_mask_secondary_irq(unsigned int irq_nr);
  56 static irqreturn_t ar7_cascade(int interrupt, void *dev);
  57 static irqreturn_t ar7_secondary_cascade(int interrupt, void *dev);
  58 static void ar7_irq_init(int base);
  59 static int ar7_irq_base;
  60
  61 static struct irq_chip ar7_irq_type = {
  62         .typename = "AR7",
  63         .name = "AR7",
  64         .unmask = ar7_unmask_irq,
  65         .mask = ar7_mask_irq,
  66 };
  67
  68 static struct irq_chip ar7_secondary_irq_type = {
  69         .name = "AR7",
  70         .unmask = ar7_unmask_secondary_irq,
  71         .mask = ar7_mask_secondary_irq,
  72 };
  73
  74 static struct irqaction ar7_cascade_action = {
  75         .handler = ar7_cascade,
  76         .name = "AR7 cascade interrupt"
  77 };
  78
  79 static struct irqaction ar7_secondary_cascade_action = {
  80         .handler = ar7_secondary_cascade,
  81         .name = "AR7 secondary cascade interrupt"
  82 };
  83
  84 static void ar7_unmask_irq(unsigned int irq)
  85 {
  86         unsigned long flags;
  87         local_irq_save(flags);
  88         /* enable the interrupt channel  bit */
  89         REG(ESR_OFFSET(irq)) = 1 << ((irq - ar7_irq_base) % 32);
  90         local_irq_restore(flags);
  91 }
  92
  93 static void ar7_mask_irq(unsigned int irq)
  94 {
  95         unsigned long flags;
  96         local_irq_save(flags);
  97         /* disable the interrupt channel bit */
  98         REG(ECR_OFFSET(irq)) = 1 << ((irq - ar7_irq_base) % 32);
  99         local_irq_restore(flags);
 100 }
 101
 102 static void ar7_unmask_secondary_irq(unsigned int irq)
 103 {
 104         unsigned long flags;
 105         local_irq_save(flags);
 106         /* enable the interrupt channel  bit */
 107         REG(SEC_ESR_OFFSET) = 1 << (irq - ar7_irq_base - 40);
 108         local_irq_restore(flags);
 109 }
 110
 111 static void ar7_mask_secondary_irq(unsigned int irq)
 112 {
 113         unsigned long flags;
 114         local_irq_save(flags);
 115         /* disable the interrupt channel bit */
 116         REG(SEC_ECR_OFFSET) = 1 << (irq - ar7_irq_base - 40);
 117         local_irq_restore(flags);
 118 }
 119
 120 void __init arch_init_irq(void) {
 121         mips_cpu_irq_init();
 122         ar7_irq_init(8);
 123 }
 124
 125 static void __init ar7_irq_init(int base)
 126 {
 127         int i;
 128         /*
 129             Disable interrupts and clear pending
 130         */
 131         REG(ECR_OFFSET(0)) = 0xffffffff;
 132         REG(ECR_OFFSET(32)) = 0xff;
 133         REG(SEC_ECR_OFFSET) = 0xffffffff;
 134         REG(CR_OFFSET(0)) = 0xffffffff;
 135         REG(CR_OFFSET(32)) = 0xff;
 136         REG(SEC_CR_OFFSET) = 0xffffffff;
 137
 138         ar7_irq_base = base;
 139
 140         for(i = 0; i < 40; i++) {
 141                 REG(CHNL_OFFSET(i)) = i;
 142                 /* Primary IRQ's */
 143                 irq_desc[i + base].status = IRQ_DISABLED;
 144                 irq_desc[i + base].action = NULL;
 145                 irq_desc[i + base].depth = 1;
 146                 irq_desc[i + base].chip = &ar7_irq_type;
 147                 /* Secondary IRQ's */
 148                 if (i < 32) {
 149                         irq_desc[i + base + 40].status = IRQ_DISABLED;
 150                         irq_desc[i + base + 40].action = NULL;
 151                         irq_desc[i + base + 40].depth = 1;
 152                         irq_desc[i + base + 40].chip = &ar7_secondary_irq_type;
 153                 }
 154         }
 155
 156         setup_irq(2, &ar7_cascade_action);
 157         setup_irq(ar7_irq_base, &ar7_secondary_cascade_action);
 158         set_c0_status(IE_IRQ0);
 159 }
 160
 161 static irqreturn_t ar7_cascade(int interrupt, void *dev)
 162 {
 163         int irq;
 164
 165         irq = (REG(PIR_OFFSET) & 0x3F);
 166         REG(CR_OFFSET(irq)) = 1 << (irq % 32);
 167
 168         do_IRQ(irq + ar7_irq_base);
 169
 170         return IRQ_HANDLED;
 171 }
 172
 173 static irqreturn_t ar7_secondary_cascade(int interrupt, void *dev)
 174 {
 175         int irq = 0, i;
 176         unsigned long status;
 177
 178         status = REG(SEC_SR_OFFSET);
 179         if (unlikely(!status)) {
 180                 spurious_interrupt();
 181                 return IRQ_NONE;
 182         }
 183
 184         for (i = 0; i < 32; i++)
 185                 if (status & (i << 1)) {
 186                         irq = i + 40;
 187                         REG(SEC_CR_OFFSET) = 1 << i;
 188                         break;
 189                 }
 190
 191         do_IRQ(irq + ar7_irq_base);
 192
 193         return IRQ_HANDLED;
 194 }
 195
 196 asmlinkage void plat_irq_dispatch(void)
 197 {
 198         unsigned int pending = read_c0_status() & read_c0_cause();
 199         if (pending & STATUSF_IP7)              /* cpu timer */
 200                 do_IRQ(7);
 201         else if (pending & STATUSF_IP2)         /* int0 hardware line */
 202                 do_IRQ(2);
 203         else
 204                 spurious_interrupt();
 205 }