Add ar7-2.6 port (marked as broken for now).
[openwrt/svn-archive/archive.git] / target / linux / ar7-2.6 / files / arch / mips / ar7 / irq.c
1 /*
2 * $Id$
3 *
4 * Copyright (C) 2006, 2007 OpenWrt.org
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
24
25 #include <asm/irq.h>
26 #include <asm/irq_cpu.h>
27 #include <asm/mipsregs.h>
28 #include <asm/ar7/ar7.h>
29
30 #define EXCEPT_OFFSET 0x80
31 #define PACE_OFFSET 0xA0
32 #define CHNLS_OFFSET 0x200
33
34 #define IRQ_NUM(irq) (irq % 40 % 32)
35 #define REG_OFFSET(irq, reg) (((irq) < 40) ? \
36 ((irq) / 32 * 0x4 + reg * 0x10) : \
37 (EXCEPT_OFFSET + reg * 0x8))
38 #define SR_OFFSET(irq) (REG_OFFSET(irq, 0))
39 #define CR_OFFSET(irq) (REG_OFFSET(irq, 1))
40 #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2))
41 #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3))
42 #define PIR_OFFSET (0x40)
43 #define MSR_OFFSET (0x44)
44 #define PM_OFFSET(irq) (REG_OFFSET(irq, 5))
45 #define TM_OFFSET(irq) (REG_OFFSET(irq, 6))
46
47 #define REG(addr) (*(volatile u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
48
49 #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
50
51 static void ar7_unmask_irq(unsigned int irq_nr);
52 static void ar7_mask_irq(unsigned int irq_nr);
53 static irqreturn_t ar7_cascade(int interrupt, void *dev);
54 void ar7_irq_init(int);
55
56 static struct irq_chip ar7_irq_type = {
57 .name = "AR7",
58 .unmask = ar7_unmask_irq,
59 .mask = ar7_mask_irq,
60 };
61
62 static int ar7_irq_base;
63
64 static struct irqaction ar7_cascade_action = {
65 .handler = ar7_cascade,
66 .name = "AR7 cascade interrupt"
67 };
68
69
70 static void ar7_unmask_irq(unsigned int irq)
71 {
72 unsigned long flags;
73 local_irq_save(flags);
74 /* enable the interrupt channel bit */
75 REG(ESR_OFFSET(irq - ar7_irq_base)) = 1 << IRQ_NUM(irq - ar7_irq_base);
76 local_irq_restore(flags);
77 }
78
79 static void ar7_mask_irq(unsigned int irq)
80 {
81 unsigned long flags;
82 local_irq_save(flags);
83 /* disable the interrupt channel bit */
84 REG(ECR_OFFSET(irq - ar7_irq_base)) = 1 << IRQ_NUM(irq - ar7_irq_base);
85 local_irq_restore(flags);
86 }
87
88 void __init arch_init_irq(void) {
89 mips_cpu_irq_init(0);
90 ar7_irq_init(8);
91 }
92
93 void __init ar7_irq_init(int base)
94 {
95 int i;
96 /*
97 Disable interrupts and clear pending
98 */
99 REG(ECR_OFFSET(0)) = 0xffffffff;
100 REG(ECR_OFFSET(32)) = 0xff;
101 REG(ECR_OFFSET(40)) = 0xffffffff;
102 REG(CR_OFFSET(0)) = 0xffffffff;
103 REG(CR_OFFSET(32)) = 0xff;
104 REG(CR_OFFSET(40)) = 0xffffffff;
105
106 for(i = 0; i < 40; i++) {
107 REG(CHNL_OFFSET(i)) = i;
108 /* Primary IRQ's */
109 irq_desc[i + base].status = IRQ_DISABLED;
110 irq_desc[i + base].action = 0;
111 irq_desc[i + base].depth = 1;
112 irq_desc[i + base].chip = &ar7_irq_type;
113 /* Secondary IRQ's */
114 if (i < 32) {
115 irq_desc[i + base + 40].status = IRQ_DISABLED;
116 irq_desc[i + base + 40].action = 0;
117 irq_desc[i + base + 40].depth = 1;
118 irq_desc[i + base + 40].chip =
119 &ar7_irq_type;
120 }
121 }
122
123 ar7_irq_base = base;
124 setup_irq(2, &ar7_cascade_action);
125 set_c0_status(IE_IRQ0);
126 }
127
128 static irqreturn_t ar7_cascade(int interrupt, void *dev)
129 {
130 int irq, i;
131 unsigned long status;
132
133 irq = (REG(PIR_OFFSET) & 0x3F);
134 if (irq == 40) return IRQ_NONE;
135 if (irq > 0) {
136 REG(CR_OFFSET(irq)) = 1 << IRQ_NUM(irq);
137 } else {
138 status = REG(SR_OFFSET(40));
139 for (i = 0; i < 32; i++) {
140 if (status & (i << 1)) {
141 irq = i + 40;
142 REG(CR_OFFSET(irq)) = 1 << i;
143 break;
144 }
145 }
146 REG(CR_OFFSET(0)) = 1;
147 }
148 return do_IRQ(irq + ar7_irq_base);
149 }
150
151 asmlinkage void plat_irq_dispatch(void)
152 {
153 unsigned int pending = read_c0_status() & read_c0_cause();
154 if (pending & STATUSF_IP7) /* cpu timer */
155 do_IRQ(7);
156 else if (pending & STATUSF_IP2) /* int0 hardware line */
157 do_IRQ(2);
158 else
159 spurious_interrupt();
160 }