target/linux/ar7-2.6/files/arch/mips/ar7/irq.c

   1 /*
   2  * $Id$
   3  *
   4  * Copyright (C) 2006, 2007 OpenWrt.org
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/ioport.h>
  24
  25 #include <asm/irq.h>
  26 #include <asm/irq_cpu.h>
  27 #include <asm/mipsregs.h>
  28 #include <asm/ar7/ar7.h>
  29
  30 #define EXCEPT_OFFSET 0x80
  31 #define PACE_OFFSET   0xA0
  32 #define CHNLS_OFFSET  0x200
  33
  34 #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
  35 #define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
  36 #define SR_OFFSET  (SEC_REG_OFFSET(0))
  37 #define CR_OFFSET(irq)  (REG_OFFSET(irq, 1))
  38 #define SEC_CR_OFFSET  (SEC_REG_OFFSET(1))
  39 #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2))
  40 #define SEC_ESR_OFFSET  (SEC_REG_OFFSET(2))
  41 #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3))
  42 #define SEC_ECR_OFFSET  (SEC_REG_OFFSET(3))
  43 #define PIR_OFFSET      (0x40)
  44 #define MSR_OFFSET      (0x44)
  45 #define PM_OFFSET(irq)  (REG_OFFSET(irq, 5))
  46 #define TM_OFFSET(irq)  (REG_OFFSET(irq, 6))
  47
  48 #define REG(addr) (*(volatile u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
  49
  50 #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
  51
  52 static void ar7_unmask_irq(unsigned int irq_nr);
  53 static void ar7_mask_irq(unsigned int irq_nr);
  54 static void ar7_unmask_secondary_irq(unsigned int irq_nr);
  55 static void ar7_mask_secondary_irq(unsigned int irq_nr);
  56 static irqreturn_t ar7_cascade(int interrupt, void *dev);
  57 static irqreturn_t ar7_secondary_cascade(int interrupt, void *dev);
  58 static void ar7_irq_init(int base);
  59 static int ar7_irq_base;
  60
  61 static struct irq_chip ar7_irq_type = {
  62         .name = "AR7",
  63         .unmask = ar7_unmask_irq,
  64         .mask = ar7_mask_irq,
  65 };
  66
  67 static struct irq_chip ar7_secondary_irq_type = {
  68         .name = "AR7",
  69         .unmask = ar7_unmask_secondary_irq,
  70         .mask = ar7_mask_secondary_irq,
  71 };
  72
  73 static struct irqaction ar7_cascade_action = {
  74         .handler = ar7_cascade,
  75         .name = "AR7 cascade interrupt"
  76 };
  77
  78 static struct irqaction ar7_secondary_cascade_action = {
  79         .handler = ar7_secondary_cascade,
  80         .name = "AR7 secondary cascade interrupt"
  81 };
  82
  83 static void ar7_unmask_irq(unsigned int irq)
  84 {
  85         unsigned long flags;
  86         local_irq_save(flags);
  87         /* enable the interrupt channel  bit */
  88         REG(ESR_OFFSET(irq)) = 1 << ((irq - ar7_irq_base) % 32);
  89         local_irq_restore(flags);
  90 }
  91
  92 static void ar7_mask_irq(unsigned int irq)
  93 {
  94         unsigned long flags;
  95         local_irq_save(flags);
  96         /* disable the interrupt channel bit */
  97         REG(ECR_OFFSET(irq)) = 1 << ((irq - ar7_irq_base) % 32);
  98         local_irq_restore(flags);
  99 }
 100
 101 static void ar7_unmask_secondary_irq(unsigned int irq)
 102 {
 103         unsigned long flags;
 104         local_irq_save(flags);
 105         /* enable the interrupt channel  bit */
 106         REG(SEC_ESR_OFFSET) = 1 << (irq - ar7_irq_base - 40);
 107         local_irq_restore(flags);
 108 }
 109
 110 static void ar7_mask_secondary_irq(unsigned int irq)
 111 {
 112         unsigned long flags;
 113         local_irq_save(flags);
 114         /* disable the interrupt channel bit */
 115         REG(SEC_ECR_OFFSET) = 1 << (irq - ar7_irq_base - 40);
 116         local_irq_restore(flags);
 117 }
 118
 119 void __init arch_init_irq(void) {
 120         mips_cpu_irq_init();
 121         ar7_irq_init(8);
 122 }
 123
 124 static void __init ar7_irq_init(int base)
 125 {
 126         int i;
 127         /*
 128             Disable interrupts and clear pending
 129         */
 130         REG(ECR_OFFSET(0)) = 0xffffffff;
 131         REG(ECR_OFFSET(32)) = 0xff;
 132         REG(SEC_ECR_OFFSET) = 0xffffffff;
 133         REG(CR_OFFSET(0)) = 0xffffffff;
 134         REG(CR_OFFSET(32)) = 0xff;
 135         REG(SEC_CR_OFFSET) = 0xffffffff;
 136
 137         ar7_irq_base = base;
 138
 139         for(i = 0; i < 40; i++) {
 140                 REG(CHNL_OFFSET(i)) = i;
 141                 /* Primary IRQ's */
 142                 irq_desc[i + base].status = IRQ_DISABLED;
 143                 irq_desc[i + base].action = NULL;
 144                 irq_desc[i + base].depth = 1;
 145                 irq_desc[i + base].chip = &ar7_irq_type;
 146                 /* Secondary IRQ's */
 147                 if (i < 32) {
 148                         irq_desc[i + base + 40].status = IRQ_DISABLED;
 149                         irq_desc[i + base + 40].action = NULL;
 150                         irq_desc[i + base + 40].depth = 1;
 151                         irq_desc[i + base + 40].chip = &ar7_secondary_irq_type;
 152                 }
 153         }
 154
 155         setup_irq(2, &ar7_cascade_action);
 156         setup_irq(ar7_irq_base, &ar7_secondary_cascade_action);
 157         set_c0_status(IE_IRQ0);
 158 }
 159
 160 static irqreturn_t ar7_cascade(int interrupt, void *dev)
 161 {
 162         int irq;
 163
 164         irq = (REG(PIR_OFFSET) & 0x3F);
 165         REG(CR_OFFSET(irq)) = 1 << (irq % 32);
 166
 167         do_IRQ(irq + ar7_irq_base);
 168
 169         return IRQ_HANDLED;
 170 }
 171
 172 static irqreturn_t ar7_secondary_cascade(int interrupt, void *dev)
 173 {
 174         int irq = 0, i;
 175         unsigned long status;
 176
 177         status = REG(SR_OFFSET);
 178         if (unlikely(!status)) {
 179                 spurious_interrupt();
 180                 return IRQ_NONE;
 181         }
 182
 183         for (i = 0; i < 32; i++)
 184                 if (status & (i << 1)) {
 185                         irq = i + 40;
 186                         REG(SEC_CR_OFFSET) = 1 << i;
 187                         break;
 188                 }
 189
 190         do_IRQ(irq + ar7_irq_base);
 191
 192         return IRQ_HANDLED;
 193 }
 194
 195 asmlinkage void plat_irq_dispatch(void)
 196 {
 197         unsigned int pending = read_c0_status() & read_c0_cause();
 198         if (pending & STATUSF_IP7)              /* cpu timer */
 199                 do_IRQ(7);
 200         else if (pending & STATUSF_IP2)         /* int0 hardware line */
 201                 do_IRQ(2);
 202         else
 203                 spurious_interrupt();
 204 }