ar7-2.6: make cpmac robust against hardware quirks when the tx or rx dma ring runs...
[openwrt/svn-archive/archive.git] / target / linux / ar7-2.6 / files / drivers / net / cpmac.c
1 /*
2 * $Id$
3 *
4 * Copyright (C) 2006, 2007 OpenWrt.org
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/moduleparam.h>
24
25 #include <linux/sched.h>
26 #include <linux/kernel.h> /* printk() */
27 #include <linux/slab.h>
28 #include <linux/errno.h>
29 #include <linux/types.h>
30 #include <linux/delay.h>
31 #include <linux/version.h>
32
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/platform_device.h>
40 #include <asm/ar7/ar7.h>
41 #include <asm/gpio.h>
42
43 MODULE_AUTHOR("Eugene Konev");
44 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
45 MODULE_LICENSE("GPL");
46
47 /* Register definitions */
48 struct cpmac_control_regs {
49 volatile u32 revision;
50 volatile u32 control;
51 volatile u32 teardown;
52 volatile u32 unused;
53 };
54
55 struct cpmac_int_regs {
56 volatile u32 stat_raw;
57 volatile u32 stat_masked;
58 volatile u32 enable;
59 volatile u32 clear;
60 };
61
62 struct cpmac_stats {
63 volatile u32 good;
64 volatile u32 bcast;
65 volatile u32 mcast;
66 volatile u32 pause;
67 volatile u32 crc_error;
68 volatile u32 align_error;
69 volatile u32 oversized;
70 volatile u32 jabber;
71 volatile u32 undersized;
72 volatile u32 fragment;
73 volatile u32 filtered;
74 volatile u32 qos_filtered;
75 volatile u32 octets;
76 };
77
78 struct cpmac_regs {
79 struct cpmac_control_regs tx_ctrl;
80 struct cpmac_control_regs rx_ctrl;
81 volatile u32 unused1[56];
82 volatile u32 mbp;
83 /* MBP bits */
84 #define MBP_RXPASSCRC 0x40000000
85 #define MBP_RXQOS 0x20000000
86 #define MBP_RXNOCHAIN 0x10000000
87 #define MBP_RXCMF 0x01000000
88 #define MBP_RXSHORT 0x00800000
89 #define MBP_RXCEF 0x00400000
90 #define MBP_RXPROMISC 0x00200000
91 #define MBP_PROMISCCHAN(chan) (((chan) & 0x7) << 16)
92 #define MBP_RXBCAST 0x00002000
93 #define MBP_BCASTCHAN(chan) (((chan) & 0x7) << 8)
94 #define MBP_RXMCAST 0x00000020
95 #define MBP_MCASTCHAN(chan) ((chan) & 0x7)
96 volatile u32 unicast_enable;
97 volatile u32 unicast_clear;
98 volatile u32 max_len;
99 volatile u32 buffer_offset;
100 volatile u32 filter_flow_threshold;
101 volatile u32 unused2[2];
102 volatile u32 flow_thre[8];
103 volatile u32 free_buffer[8];
104 volatile u32 mac_control;
105 #define MAC_TXPTYPE 0x00000200
106 #define MAC_TXPACE 0x00000040
107 #define MAC_MII 0x00000020
108 #define MAC_TXFLOW 0x00000010
109 #define MAC_RXFLOW 0x00000008
110 #define MAC_MTEST 0x00000004
111 #define MAC_LOOPBACK 0x00000002
112 #define MAC_FDX 0x00000001
113 volatile u32 mac_status;
114 #define MACST_QOS 0x4
115 #define MACST_RXFLOW 0x2
116 #define MACST_TXFLOW 0x1
117 volatile u32 emc_control;
118 volatile u32 unused3;
119 struct cpmac_int_regs tx_int;
120 volatile u32 mac_int_vector;
121 /* Int Status bits */
122 #define INTST_STATUS 0x80000
123 #define INTST_HOST 0x40000
124 #define INTST_RX 0x20000
125 #define INTST_TX 0x10000
126 volatile u32 mac_eoi_vector;
127 volatile u32 unused4[2];
128 struct cpmac_int_regs rx_int;
129 volatile u32 mac_int_stat_raw;
130 volatile u32 mac_int_stat_masked;
131 volatile u32 mac_int_enable;
132 volatile u32 mac_int_clear;
133 volatile u32 mac_addr_low[8];
134 volatile u32 mac_addr_mid;
135 volatile u32 mac_addr_high;
136 volatile u32 mac_hash_low;
137 volatile u32 mac_hash_high;
138 volatile u32 boff_test;
139 volatile u32 pac_test;
140 volatile u32 rx_pause;
141 volatile u32 tx_pause;
142 volatile u32 unused5[2];
143 struct cpmac_stats rx_stats;
144 struct cpmac_stats tx_stats;
145 volatile u32 unused6[232];
146 volatile u32 tx_ptr[8];
147 volatile u32 rx_ptr[8];
148 volatile u32 tx_ack[8];
149 volatile u32 rx_ack[8];
150
151 };
152
153 struct cpmac_mdio_regs {
154 volatile u32 version;
155 volatile u32 control;
156 #define MDIOC_IDLE 0x80000000
157 #define MDIOC_ENABLE 0x40000000
158 #define MDIOC_PREAMBLE 0x00100000
159 #define MDIOC_FAULT 0x00080000
160 #define MDIOC_FAULTDETECT 0x00040000
161 #define MDIOC_INTTEST 0x00020000
162 #define MDIOC_CLKDIV(div) ((div) & 0xff)
163 volatile u32 alive;
164 volatile u32 link;
165 struct cpmac_int_regs link_int;
166 struct cpmac_int_regs user_int;
167 u32 unused[20];
168 volatile u32 access;
169 #define MDIO_BUSY 0x80000000
170 #define MDIO_WRITE 0x40000000
171 #define MDIO_REG(reg) (((reg) & 0x1f) << 21)
172 #define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
173 #define MDIO_DATA(data) ((data) & 0xffff)
174 volatile u32 physel;
175 };
176
177 /* Descriptor */
178 struct cpmac_desc {
179 u32 hw_next;
180 u32 hw_data;
181 u16 buflen;
182 u16 bufflags;
183 u16 datalen;
184 u16 dataflags;
185 /* Flags bits */
186 #define CPMAC_SOP 0x8000
187 #define CPMAC_EOP 0x4000
188 #define CPMAC_OWN 0x2000
189 #define CPMAC_EOQ 0x1000
190 u32 jiffies;
191 struct sk_buff *skb;
192 struct cpmac_desc *next;
193 };
194
195 struct cpmac_priv {
196 struct net_device_stats stats;
197 spinlock_t lock;
198 struct sk_buff *skb_pool;
199 int free_skbs;
200 struct cpmac_desc *rx_head, *rx_tail;
201 int tx_head, tx_tail;
202 struct cpmac_desc *desc_ring;
203 struct cpmac_regs *regs;
204 struct mii_bus *mii_bus;
205 struct phy_device *phy;
206 char phy_name[BUS_ID_SIZE];
207 struct plat_cpmac_data *config;
208 int oldlink, oldspeed, oldduplex;
209 u32 msg_enable;
210 struct net_device *dev;
211 struct work_struct alloc_work;
212 struct work_struct reset_work;
213 };
214
215 static irqreturn_t cpmac_irq(int, void *);
216 static int cpmac_stop(struct net_device *dev);
217 static int cpmac_open(struct net_device *dev);
218
219 #define CPMAC_LOW_THRESH 8
220 #define CPMAC_ALLOC_SIZE 32
221 #define CPMAC_SKB_SIZE 1536
222 #define CPMAC_TX_RING_SIZE 8
223 #define CPMAC_RX_RING_SIZE 16
224
225 #ifdef CPMAC_DEBUG
226 static void cpmac_dump_regs(u32 *base, int count)
227 {
228 int i;
229 for (i = 0; i < (count + 3) / 4; i++) {
230 if (i % 4 == 0) printk("\nCPMAC[0x%04x]:", i * 4);
231 printk(" 0x%08x", *(base + i));
232 }
233 printk("\n");
234 }
235 #endif
236
237 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
238 {
239 struct cpmac_mdio_regs *regs = (struct cpmac_mdio_regs *)bus->priv;
240 volatile u32 val;
241
242 while ((val = regs->access) & MDIO_BUSY);
243 regs->access = MDIO_BUSY | MDIO_REG(regnum & 0x1f) |
244 MDIO_PHY(phy_id & 0x1f);
245 while ((val = regs->access) & MDIO_BUSY);
246
247 return val & 0xffff;
248 }
249
250 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 val)
251 {
252 struct cpmac_mdio_regs *regs = (struct cpmac_mdio_regs *)bus->priv;
253 volatile u32 tmp;
254
255 while ((tmp = regs->access) & MDIO_BUSY);
256 regs->access = MDIO_BUSY | MDIO_WRITE |
257 MDIO_REG(regnum & 0x1f) | MDIO_PHY(phy_id & 0x1f) |
258 val;
259
260 return 0;
261 }
262
263 static int cpmac_mdio_reset(struct mii_bus *bus)
264 {
265 struct cpmac_mdio_regs *regs = (struct cpmac_mdio_regs *)bus->priv;
266
267 ar7_device_reset(AR7_RESET_BIT_MDIO);
268 regs->control = MDIOC_ENABLE |
269 MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1);
270
271 return 0;
272 }
273
274 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
275
276 static struct mii_bus cpmac_mii = {
277 .name = "cpmac-mii",
278 .read = cpmac_mdio_read,
279 .write = cpmac_mdio_write,
280 .reset = cpmac_mdio_reset,
281 .irq = mii_irqs,
282 };
283
284 static int cpmac_config(struct net_device *dev, struct ifmap *map)
285 {
286 if (dev->flags & IFF_UP)
287 return -EBUSY;
288
289 /* Don't allow changing the I/O address */
290 if (map->base_addr != dev->base_addr)
291 return -EOPNOTSUPP;
292
293 /* ignore other fields */
294 return 0;
295 }
296
297 static int cpmac_set_mac_address(struct net_device *dev, void *addr)
298 {
299 struct sockaddr *sa = addr;
300
301 if (dev->flags & IFF_UP)
302 return -EBUSY;
303
304 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
305
306 return 0;
307 }
308
309 static void cpmac_set_multicast_list(struct net_device *dev)
310 {
311 struct dev_mc_list *iter;
312 int i;
313 int hash, tmp;
314 int hashlo = 0, hashhi = 0;
315 struct cpmac_priv *priv = netdev_priv(dev);
316
317 if(dev->flags & IFF_PROMISC) {
318 priv->regs->mbp &= ~MBP_PROMISCCHAN(0); /* promisc channel 0 */
319 priv->regs->mbp |= MBP_RXPROMISC;
320 } else {
321 priv->regs->mbp &= ~MBP_RXPROMISC;
322 if(dev->flags & IFF_ALLMULTI) {
323 /* enable all multicast mode */
324 priv->regs->mac_hash_low = 0xffffffff;
325 priv->regs->mac_hash_high = 0xffffffff;
326 } else {
327 for(i = 0, iter = dev->mc_list; i < dev->mc_count;
328 i++, iter = iter->next) {
329 hash = 0;
330 tmp = iter->dmi_addr[0];
331 hash ^= (tmp >> 2) ^ (tmp << 4);
332 tmp = iter->dmi_addr[1];
333 hash ^= (tmp >> 4) ^ (tmp << 2);
334 tmp = iter->dmi_addr[2];
335 hash ^= (tmp >> 6) ^ tmp;
336 tmp = iter->dmi_addr[4];
337 hash ^= (tmp >> 2) ^ (tmp << 4);
338 tmp = iter->dmi_addr[5];
339 hash ^= (tmp >> 4) ^ (tmp << 2);
340 tmp = iter->dmi_addr[6];
341 hash ^= (tmp >> 6) ^ tmp;
342 hash &= 0x3f;
343 if(hash < 32) {
344 hashlo |= 1<<hash;
345 } else {
346 hashhi |= 1<<(hash - 32);
347 }
348 }
349
350 priv->regs->mac_hash_low = hashlo;
351 priv->regs->mac_hash_high = hashhi;
352 }
353 }
354 }
355
356 static struct sk_buff *cpmac_get_skb(struct net_device *dev)
357 {
358 struct sk_buff *skb;
359 struct cpmac_priv *priv = netdev_priv(dev);
360
361 skb = priv->skb_pool;
362 if (likely(skb))
363 priv->skb_pool = skb->next;
364
365 if (likely(priv->free_skbs))
366 priv->free_skbs--;
367
368 if (priv->free_skbs < CPMAC_LOW_THRESH)
369 schedule_work(&priv->alloc_work);
370
371 return skb;
372 }
373
374 static void cpmac_rx(struct net_device *dev, int channel)
375 {
376 char *data;
377 struct sk_buff *skb;
378 struct cpmac_desc *desc;
379 struct cpmac_desc *start;
380 struct cpmac_priv *priv = netdev_priv(dev);
381
382 spin_lock(&priv->lock);
383 if (unlikely(!priv->rx_head))
384 return;
385
386
387 desc = priv->rx_tail->next;
388 dma_cache_inv((u32)desc, 16);
389
390 start = priv->rx_tail;
391 while((desc->dataflags & CPMAC_OWN) == 0) {
392 priv->regs->rx_ack[0] = virt_to_phys(desc);
393 if (unlikely(!desc->datalen)) {
394 if (printk_ratelimit())
395 printk(KERN_NOTICE "%s: rx: spurious interrupt\n",
396 dev->name);
397 priv->stats.rx_errors++;
398 goto out;
399 }
400
401 skb = cpmac_get_skb(dev);
402 if (likely(skb)) {
403 data = (char *)phys_to_virt(desc->hw_data);
404 dma_cache_inv((u32)data, desc->datalen);
405 skb_put(desc->skb, desc->datalen);
406 desc->skb->protocol = eth_type_trans(desc->skb, dev);
407 desc->skb->ip_summed = CHECKSUM_NONE;
408 priv->stats.rx_packets++;
409 priv->stats.rx_bytes += desc->datalen;
410 netif_rx(desc->skb);
411 desc->skb = skb;
412 } else {
413 if (printk_ratelimit())
414 printk(KERN_NOTICE "%s: rx: no free skbs, dropping packet\n",
415 dev->name);
416 priv->regs->rx_ptr[0] = virt_to_phys(desc);
417 priv->stats.rx_dropped++;
418 }
419 desc->hw_data = virt_to_phys(desc->skb->data);
420 desc->buflen = CPMAC_SKB_SIZE;
421 desc->dataflags = CPMAC_OWN;
422 desc->hw_next = 0;
423 dma_cache_wback((u32)desc, 16);
424
425 priv->rx_tail->hw_next = virt_to_phys(desc);
426 priv->rx_tail->dataflags = CPMAC_OWN;
427 dma_cache_wback((u32)priv->rx_tail, 16);
428
429 priv->rx_tail = desc;
430 desc = desc->next;
431 dma_cache_inv((u32)desc, 16);
432 if (start == desc) {
433 printk("Somebody set up us the bomb!!\n");
434 break;
435 }
436 }
437 out:
438 priv->rx_head = desc;
439 priv->regs->rx_ptr[0] = virt_to_phys(desc);
440 spin_unlock(&priv->lock);
441 }
442
443 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)
444 static void
445 cpmac_alloc_skbs(struct work_struct *work)
446 {
447 struct cpmac_priv *priv = container_of(work, struct cpmac_priv,
448 alloc_work);
449 #else
450 static void
451 cpmac_alloc_skbs(void *data)
452 {
453 struct net_device *dev = (struct net_device*)data;
454 struct cpmac_priv *priv = netdev_priv(dev);
455 #endif
456 unsigned long flags;
457 int i, num_skbs = 0;
458 struct sk_buff *skb, *skbs = NULL;
459
460 for (i = 0; i < CPMAC_ALLOC_SIZE; i++) {
461 skb = alloc_skb(CPMAC_SKB_SIZE + 2, GFP_KERNEL);
462 if (!skb)
463 break;
464 skb->next = skbs;
465 skb_reserve(skb, 2);
466 skb->dev = priv->dev;
467 num_skbs++;
468 skbs = skb;
469 }
470
471 if (skbs) {
472 spin_lock_irqsave(&priv->lock, flags);
473 for (skb = priv->skb_pool; skb && skb->next; skb = skb->next);
474 if (!skb) {
475 priv->skb_pool = skbs;
476 } else {
477 skb->next = skbs;
478 }
479 priv->free_skbs += num_skbs;
480 spin_unlock_irqrestore(&priv->lock, flags);
481 #ifdef CPMAC_DEBUG
482 printk("%s: allocated %d skbs\n", priv->dev->name, num_skbs);
483 #endif
484 }
485 }
486
487 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
488 {
489 unsigned long flags;
490 int len, chan;
491 struct cpmac_desc *desc;
492 struct cpmac_priv *priv = netdev_priv(dev);
493
494 len = skb->len;
495 if (unlikely(len < ETH_ZLEN)) {
496 if (unlikely(skb_padto(skb, ETH_ZLEN))) {
497 if (printk_ratelimit())
498 printk(KERN_NOTICE "%s: padding failed, dropping\n",
499 dev->name);
500 spin_lock_irqsave(&priv->lock, flags);
501 priv->stats.tx_dropped++;
502 spin_unlock_irqrestore(&priv->lock, flags);
503 return -ENOMEM;
504 }
505 len = ETH_ZLEN;
506 }
507 spin_lock_irqsave(&priv->lock, flags);
508 chan = priv->tx_tail++;
509 priv->tx_tail %= 8;
510 if (priv->tx_tail == priv->tx_head)
511 netif_stop_queue(dev);
512
513 desc = &priv->desc_ring[chan];
514 dma_cache_inv((u32)desc, 16);
515 if (desc->dataflags & CPMAC_OWN) {
516 printk(KERN_NOTICE "%s: tx dma ring full, dropping\n", dev->name);
517 spin_lock_irqsave(&priv->lock, flags);
518 priv->stats.tx_dropped++;
519 spin_unlock_irqrestore(&priv->lock, flags);
520 return -ENOMEM;
521 }
522
523 dev->trans_start = jiffies;
524 desc->jiffies = dev->trans_start;
525 spin_unlock_irqrestore(&priv->lock, flags);
526
527 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
528 desc->skb = skb;
529 desc->hw_data = virt_to_phys(skb->data);
530 dma_cache_wback((u32)skb->data, len);
531 desc->buflen = len;
532 desc->datalen = len;
533 desc->hw_next = 0;
534 dma_cache_wback((u32)desc, 16);
535 priv->regs->tx_ptr[chan] = virt_to_phys(desc);
536 return 0;
537 }
538
539 static void cpmac_end_xmit(struct net_device *dev, int channel)
540 {
541 struct cpmac_desc *desc;
542 struct cpmac_priv *priv = netdev_priv(dev);
543
544 spin_lock(&priv->lock);
545 desc = &priv->desc_ring[channel];
546 priv->regs->tx_ack[channel] = virt_to_phys(desc);
547 if (likely(desc->skb)) {
548 priv->stats.tx_packets++;
549 priv->stats.tx_bytes += desc->skb->len;
550 dev_kfree_skb_irq(desc->skb);
551 if (priv->tx_head == channel) {
552 while ((desc->dataflags & CPMAC_OWN) == 0) {
553 priv->tx_head++;
554 priv->tx_head %= 8;
555 if (priv->tx_head == priv->tx_tail)
556 break;
557 desc = &priv->desc_ring[priv->tx_head];
558 }
559 }
560 if (netif_queue_stopped(dev))
561 netif_wake_queue(dev);
562 } else {
563 if (printk_ratelimit())
564 printk(KERN_NOTICE "%s: end_xmit: spurious interrupt\n",
565 dev->name);
566 }
567 spin_unlock(&priv->lock);
568 }
569
570 static void cpmac_reset(struct net_device *dev)
571 {
572 int i;
573 struct cpmac_priv *priv = netdev_priv(dev);
574
575 ar7_device_reset(priv->config->reset_bit);
576 priv->regs->rx_ctrl.control &= ~1;
577 priv->regs->tx_ctrl.control &= ~1;
578 for (i = 0; i < 8; i++) {
579 priv->regs->tx_ptr[i] = 0;
580 priv->regs->rx_ptr[i] = 0;
581 }
582 priv->regs->mac_control &= ~MAC_MII; /* disable mii */
583 }
584
585 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)
586 static void
587 cpmac_full_reset(struct work_struct *work)
588 {
589 struct cpmac_priv *priv = container_of(work, struct cpmac_priv,
590 alloc_work);
591 struct net_device *dev = priv->dev;
592 #else
593 static void
594 cpmac_full_reset(void *data)
595 {
596 struct net_device *dev = (struct net_device*)data;
597 #endif
598
599 cpmac_stop(dev);
600 cpmac_open(dev);
601 }
602
603
604 static irqreturn_t cpmac_irq(int irq, void *dev_id)
605 {
606 struct net_device *dev = (struct net_device *)dev_id;
607 struct cpmac_priv *priv = netdev_priv(dev);
608 u32 status;
609
610 if (!dev)
611 return IRQ_NONE;
612
613 status = priv->regs->mac_int_vector;
614
615 if (status & INTST_TX) {
616 cpmac_end_xmit(dev, (status & 7));
617 }
618
619 if (status & INTST_RX) {
620 cpmac_rx(dev, (status >> 8) & 7);
621 }
622
623 if (unlikely(status & INTST_HOST)) { /* host interrupt ??? */
624 printk("%s: host int, something bad happened - mac status: 0x%08x\n", dev->name, priv->regs->mac_status);
625
626 /* try to recover */
627 cpmac_reset(dev);
628 schedule_work(&priv->reset_work);
629 }
630
631 if (unlikely(status & INTST_STATUS)) { /* status interrupt ??? */
632 printk("%s: status int, what are we gonna do?\n", dev->name);
633 }
634
635 priv->regs->mac_eoi_vector = 0;
636
637 return IRQ_HANDLED;
638 }
639
640 static void cpmac_tx_timeout(struct net_device *dev)
641 {
642 struct cpmac_priv *priv = netdev_priv(dev);
643 struct cpmac_desc *desc;
644
645 priv->stats.tx_errors++;
646 desc = &priv->desc_ring[priv->tx_head++];
647 priv->tx_head %= 8;
648 printk("Transmit timeout at %ld, latency %ld\n", jiffies,
649 jiffies - desc->jiffies);
650 if (desc->skb)
651 dev_kfree_skb(desc->skb);
652 netif_wake_queue(dev);
653 }
654
655 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
656 {
657 struct cpmac_priv *priv = netdev_priv(dev);
658 if (!(netif_running(dev)))
659 return -EINVAL;
660 if (!priv->phy)
661 return -EINVAL;
662 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
663 }
664
665 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
666 {
667 struct cpmac_priv *priv = netdev_priv(dev);
668
669 if (priv->phy)
670 return phy_ethtool_gset(priv->phy, cmd);
671
672 return -EINVAL;
673 }
674
675 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
676 {
677 struct cpmac_priv *priv = netdev_priv(dev);
678
679 if (!capable(CAP_NET_ADMIN))
680 return -EPERM;
681
682 if (priv->phy)
683 return phy_ethtool_sset(priv->phy, cmd);
684
685 return -EINVAL;
686 }
687
688 static void cpmac_get_drvinfo(struct net_device *dev,
689 struct ethtool_drvinfo *info)
690 {
691 strcpy(info->driver, "cpmac");
692 strcpy(info->version, "0.0.3");
693 info->fw_version[0] = '\0';
694 sprintf(info->bus_info, "%s", "cpmac");
695 info->regdump_len = 0;
696 }
697
698 static const struct ethtool_ops cpmac_ethtool_ops = {
699 .get_settings = cpmac_get_settings,
700 .set_settings = cpmac_set_settings,
701 .get_drvinfo = cpmac_get_drvinfo,
702 .get_link = ethtool_op_get_link,
703 };
704
705 static struct net_device_stats *cpmac_stats(struct net_device *dev)
706 {
707 struct cpmac_priv *priv = netdev_priv(dev);
708
709 if (netif_device_present(dev))
710 return &priv->stats;
711
712 return NULL;
713 }
714
715 static int cpmac_change_mtu(struct net_device *dev, int mtu)
716 {
717 unsigned long flags;
718 struct cpmac_priv *priv = netdev_priv(dev);
719 spinlock_t *lock = &priv->lock;
720
721 if ((mtu < 68) || (mtu > 1500))
722 return -EINVAL;
723
724 spin_lock_irqsave(lock, flags);
725 dev->mtu = mtu;
726 spin_unlock_irqrestore(lock, flags);
727
728 return 0;
729 }
730
731 static void cpmac_adjust_link(struct net_device *dev)
732 {
733 struct cpmac_priv *priv = netdev_priv(dev);
734 unsigned long flags;
735 int new_state = 0;
736
737 spin_lock_irqsave(&priv->lock, flags);
738 if (priv->phy->link) {
739 if (priv->phy->duplex != priv->oldduplex) {
740 new_state = 1;
741 priv->oldduplex = priv->phy->duplex;
742 }
743
744 if (priv->phy->speed != priv->oldspeed) {
745 new_state = 1;
746 priv->oldspeed = priv->phy->speed;
747 }
748
749 if (!priv->oldlink) {
750 new_state = 1;
751 priv->oldlink = 1;
752 netif_schedule(dev);
753 }
754 } else if (priv->oldlink) {
755 new_state = 1;
756 priv->oldlink = 0;
757 priv->oldspeed = 0;
758 priv->oldduplex = -1;
759 }
760
761 if (new_state)
762 phy_print_status(priv->phy);
763
764 spin_unlock_irqrestore(&priv->lock, flags);
765 }
766
767 static int cpmac_open(struct net_device *dev)
768 {
769 int i, size, res;
770 struct cpmac_priv *priv = netdev_priv(dev);
771 struct cpmac_desc *desc;
772 struct sk_buff *skb;
773
774 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)
775 priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link,
776 0, PHY_INTERFACE_MODE_MII);
777 #else
778 priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link, 0);
779 #endif
780 if (IS_ERR(priv->phy)) {
781 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
782 return PTR_ERR(priv->phy);
783 }
784
785 if (!request_mem_region(dev->mem_start, dev->mem_end -
786 dev->mem_start, dev->name)) {
787 printk("%s: failed to request registers\n",
788 dev->name);
789 res = -ENXIO;
790 goto fail_reserve;
791 }
792
793 priv->regs = ioremap_nocache(dev->mem_start, dev->mem_end -
794 dev->mem_start);
795 if (!priv->regs) {
796 printk("%s: failed to remap registers\n", dev->name);
797 res = -ENXIO;
798 goto fail_remap;
799 }
800
801 priv->rx_head = NULL;
802 size = sizeof(struct cpmac_desc) * (CPMAC_RX_RING_SIZE +
803 CPMAC_TX_RING_SIZE);
804 priv->desc_ring = (struct cpmac_desc *)kmalloc(size, GFP_KERNEL);
805 if (!priv->desc_ring) {
806 res = -ENOMEM;
807 goto fail_alloc;
808 }
809
810 memset((char *)priv->desc_ring, 0, size);
811
812 priv->skb_pool = NULL;
813 priv->free_skbs = 0;
814 priv->rx_head = &priv->desc_ring[CPMAC_TX_RING_SIZE];
815
816 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)
817 INIT_WORK(&priv->alloc_work, cpmac_alloc_skbs);
818 INIT_WORK(&priv->reset_work, cpmac_full_reset);
819 #else
820 INIT_WORK(&priv->alloc_work, cpmac_alloc_skbs, dev);
821 INIT_WORK(&priv->reset_work, cpmac_full_reset, dev);
822 #endif
823 schedule_work(&priv->alloc_work);
824 flush_scheduled_work();
825
826 for (i = 0; i < CPMAC_RX_RING_SIZE; i++) {
827 desc = &priv->rx_head[i];
828 skb = cpmac_get_skb(dev);
829 if (!skb) {
830 res = -ENOMEM;
831 goto fail_desc;
832 }
833 desc->skb = skb;
834 desc->hw_data = virt_to_phys(skb->data);
835 desc->buflen = CPMAC_SKB_SIZE;
836 desc->dataflags = CPMAC_OWN;
837 desc->next = &priv->rx_head[i + 1];
838 desc->hw_next = virt_to_phys(desc->next);
839 dma_cache_wback((u32)desc, 16);
840 }
841 priv->rx_tail = &priv->rx_head[CPMAC_RX_RING_SIZE - 1];
842 priv->rx_tail->next = priv->rx_head;
843 priv->rx_tail->hw_next = 0;
844
845 cpmac_reset(dev);
846 for (i = 0; i < 8; i++)
847 priv->regs->tx_ptr[i] = 0;
848 priv->regs->rx_ptr[0] = virt_to_phys(priv->rx_head);
849
850 priv->regs->mbp = MBP_RXSHORT | MBP_RXBCAST | MBP_RXMCAST;
851 priv->regs->unicast_enable = 0x1;
852 priv->regs->unicast_clear = 0xfe;
853 priv->regs->buffer_offset = 0;
854 for (i = 0; i < 8; i++)
855 priv->regs->mac_addr_low[i] = dev->dev_addr[5];
856 priv->regs->mac_addr_mid = dev->dev_addr[4];
857 priv->regs->mac_addr_high = dev->dev_addr[0] | (dev->dev_addr[1] << 8)
858 | (dev->dev_addr[2] << 16) | (dev->dev_addr[3] << 24);
859 priv->regs->max_len = CPMAC_SKB_SIZE;
860 priv->regs->rx_int.enable = 0x1;
861 priv->regs->rx_int.clear = 0xfe;
862 priv->regs->tx_int.enable = 0xff;
863 priv->regs->tx_int.clear = 0;
864 priv->regs->mac_int_enable = 3;
865 priv->regs->mac_int_clear = 0xfc;
866
867 if((res = request_irq(dev->irq, cpmac_irq, SA_INTERRUPT,
868 dev->name, dev))) {
869 printk("%s: failed to obtain irq\n", dev->name);
870 goto fail_irq;
871 }
872
873 priv->regs->rx_ctrl.control |= 1;
874 priv->regs->tx_ctrl.control |= 1;
875 priv->regs->mac_control |= MAC_MII | MAC_FDX;
876
877 priv->phy->state = PHY_CHANGELINK;
878 phy_start(priv->phy);
879
880 netif_start_queue(dev);
881 return 0;
882
883 fail_irq:
884 fail_desc:
885 for (i = 0; i < CPMAC_RX_RING_SIZE; i++)
886 if (priv->rx_head[i].skb)
887 kfree_skb(priv->rx_head[i].skb);
888 fail_alloc:
889 kfree(priv->desc_ring);
890
891 for (skb = priv->skb_pool; skb; skb = priv->skb_pool) {
892 priv->skb_pool = skb->next;
893 kfree_skb(skb);
894 }
895
896 iounmap(priv->regs);
897
898 fail_remap:
899 release_mem_region(dev->mem_start, dev->mem_end -
900 dev->mem_start);
901
902 fail_reserve:
903 phy_disconnect(priv->phy);
904
905 return res;
906 }
907
908 static int cpmac_stop(struct net_device *dev)
909 {
910 int i;
911 struct sk_buff *skb;
912 struct cpmac_priv *priv = netdev_priv(dev);
913
914 netif_stop_queue(dev);
915
916 phy_stop(priv->phy);
917 phy_disconnect(priv->phy);
918 priv->phy = NULL;
919
920 cpmac_reset(dev);
921
922 for (i = 0; i < 8; i++) {
923 priv->regs->rx_ptr[i] = 0;
924 priv->regs->tx_ptr[i] = 0;
925 priv->regs->mbp = 0;
926 }
927
928 free_irq(dev->irq, dev);
929 release_mem_region(dev->mem_start, dev->mem_end -
930 dev->mem_start);
931
932 cancel_delayed_work(&priv->alloc_work);
933 flush_scheduled_work();
934
935 priv->rx_head = &priv->desc_ring[CPMAC_TX_RING_SIZE];
936 for (i = 0; i < CPMAC_RX_RING_SIZE; i++)
937 if (priv->rx_head[i].skb)
938 kfree_skb(priv->rx_head[i].skb);
939
940 kfree(priv->desc_ring);
941
942 for (skb = priv->skb_pool; skb; skb = priv->skb_pool) {
943 priv->skb_pool = skb->next;
944 kfree_skb(skb);
945 }
946
947 return 0;
948 }
949
950 static int external_switch = 0;
951
952 static int __devinit cpmac_probe(struct platform_device *pdev)
953 {
954 int i, rc, phy_id;
955 struct resource *res;
956 struct cpmac_priv *priv;
957 struct net_device *dev;
958 struct plat_cpmac_data *pdata;
959
960 if (strcmp(pdev->name, "cpmac") != 0)
961 return -ENODEV;
962
963 pdata = pdev->dev.platform_data;
964
965 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
966 if (!(pdata->phy_mask & (1 << phy_id)))
967 continue;
968 if (!cpmac_mii.phy_map[phy_id])
969 continue;
970 break;
971 }
972
973 if (phy_id == PHY_MAX_ADDR) {
974 if (external_switch) {
975 phy_id = 0;
976 } else {
977 printk("cpmac: no PHY present\n");
978 return -ENODEV;
979 }
980 }
981
982 dev = alloc_etherdev(sizeof(struct cpmac_priv));
983
984 if (!dev) {
985 printk(KERN_ERR "cpmac: Unable to allocate net_device structure!\n");
986 return -ENOMEM;
987 }
988
989 SET_MODULE_OWNER(dev);
990 platform_set_drvdata(pdev, dev);
991 priv = netdev_priv(dev);
992
993 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
994 if (!res) {
995 rc = -ENODEV;
996 goto fail;
997 }
998
999 dev->mem_start = res->start;
1000 dev->mem_end = res->end;
1001 dev->irq = platform_get_irq_byname(pdev, "irq");
1002
1003 dev->mtu = 1500;
1004 dev->open = cpmac_open;
1005 dev->stop = cpmac_stop;
1006 dev->set_config = cpmac_config;
1007 dev->hard_start_xmit = cpmac_start_xmit;
1008 dev->do_ioctl = cpmac_ioctl;
1009 dev->get_stats = cpmac_stats;
1010 dev->change_mtu = cpmac_change_mtu;
1011 dev->set_mac_address = cpmac_set_mac_address;
1012 dev->set_multicast_list = cpmac_set_multicast_list;
1013 dev->tx_timeout = cpmac_tx_timeout;
1014 dev->ethtool_ops = &cpmac_ethtool_ops;
1015
1016 memset(priv, 0, sizeof(struct cpmac_priv));
1017 spin_lock_init(&priv->lock);
1018 priv->msg_enable = netif_msg_init(NETIF_MSG_WOL, 0x3fff);
1019 priv->config = pdata;
1020 priv->dev = dev;
1021 memcpy(dev->dev_addr, priv->config->dev_addr, sizeof(dev->dev_addr));
1022 if (phy_id == 31) {
1023 snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT,
1024 cpmac_mii.id, phy_id);
1025 } else {
1026 snprintf(priv->phy_name, BUS_ID_SIZE, "fixed@%d:%d", 100, 1);
1027 }
1028
1029 if ((rc = register_netdev(dev))) {
1030 printk("cpmac: error %i registering device %s\n",
1031 rc, dev->name);
1032 goto fail;
1033 }
1034
1035 printk("cpmac: device %s (regs: %p, irq: %d, phy: %s, mac: ",
1036 dev->name, (u32 *)dev->mem_start, dev->irq,
1037 priv->phy_name);
1038 for (i = 0; i < 6; i++) {
1039 printk("%02x", dev->dev_addr[i]);
1040 if (i < 5) printk(":");
1041 else printk(")\n");
1042 }
1043
1044 return 0;
1045
1046 fail:
1047 free_netdev(dev);
1048 return rc;
1049 }
1050
1051 static int __devexit cpmac_remove(struct platform_device *pdev)
1052 {
1053 struct net_device *dev = platform_get_drvdata(pdev);
1054 unregister_netdev(dev);
1055 free_netdev(dev);
1056 return 0;
1057 }
1058
1059 static struct platform_driver cpmac_driver = {
1060 .driver.name = "cpmac",
1061 .probe = cpmac_probe,
1062 .remove = cpmac_remove,
1063 };
1064
1065 int __devinit cpmac_init(void)
1066 {
1067 volatile u32 mask;
1068 int i, res;
1069 cpmac_mii.priv = (struct cpmac_mdio_regs *)
1070 ioremap_nocache(AR7_REGS_MDIO, sizeof(struct cpmac_mdio_regs));
1071
1072 if (!cpmac_mii.priv) {
1073 printk("Can't ioremap mdio registers\n");
1074 return -ENXIO;
1075 }
1076
1077 #warning FIXME: unhardcode gpio&reset bits
1078 ar7_gpio_disable(26);
1079 ar7_gpio_disable(27);
1080 ar7_device_reset(17);
1081 ar7_device_reset(21);
1082 ar7_device_reset(26);
1083
1084 cpmac_mii.reset(&cpmac_mii);
1085
1086 for (i = 0; i < 300000; i++) {
1087 mask = ((struct cpmac_mdio_regs *)cpmac_mii.priv)->alive;
1088 if (mask)
1089 break;
1090 }
1091
1092 mask &= 0x7fffffff;
1093 if (mask & (mask - 1)) {
1094 external_switch = 1;
1095 mask = 0;
1096 }
1097
1098 cpmac_mii.phy_mask = ~(mask | 0x80000000);
1099
1100 res = mdiobus_register(&cpmac_mii);
1101 if (res)
1102 goto fail_mii;
1103
1104 res = platform_driver_register(&cpmac_driver);
1105 if (res)
1106 goto fail_cpmac;
1107
1108 return 0;
1109
1110 fail_cpmac:
1111 mdiobus_unregister(&cpmac_mii);
1112
1113 fail_mii:
1114 iounmap(cpmac_mii.priv);
1115
1116 return res;
1117 }
1118
1119 void __devexit cpmac_exit(void)
1120 {
1121 platform_driver_unregister(&cpmac_driver);
1122 mdiobus_unregister(&cpmac_mii);
1123 }
1124
1125 module_init(cpmac_init);
1126 module_exit(cpmac_exit);