ar7: speed up irq handlers, fix asm/ar7/ar7.h
[openwrt/svn-archive/archive.git] / target / linux / ar7-2.6 / files / include / asm-mips / ar7 / ar7.h
1 /*
2 * $Id$
3 *
4 * Copyright (C) 2006, 2007 OpenWrt.org
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 #ifndef __AR7_H__
22 #define __AR7_H__
23
24 #include <linux/delay.h>
25 #include <asm/addrspace.h>
26 #include <asm/io.h>
27
28 #define AR7_REGS_BASE 0x08610000
29
30 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
31 #define AR7_REGS_EMIF (AR7_REGS_BASE + 0x0800)
32 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
33 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
34 #define AR7_REGS_WDT (AR7_REGS_BASE + 0x0b00)
35 #define AR7_REGS_TIMER0 (AR7_REGS_BASE + 0x0c00)
36 #define AR7_REGS_TIMER1 (AR7_REGS_BASE + 0x0d00)
37 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
38 #define AR7_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
39 #define AR7_REGS_I2C (AR7_REGS_BASE + 0x1000)
40 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
41 #define AR7_REGS_DMA (AR7_REGS_BASE + 0x1400)
42 #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
43 #define AR7_REGS_BIST (AR7_REGS_BASE + 0x1700)
44 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
45 #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1A00)
46 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1C00)
47 #define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1E00)
48 #define AR7_REGS_FSER (AR7_REGS_BASE + 0x2000)
49 #define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
50 #define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
51
52 #define AR7_RESET_PEREPHERIAL 0x0
53 #define AR7_RESET_SOFTWARE 0x4
54 #define AR7_RESET_STATUS 0x8
55
56 #define AR7_RESET_BIT_MDIO 22
57
58 /* GPIO control registers */
59 #define AR7_GPIO_INPUT 0x0
60 #define AR7_GPIO_OUTPUT 0x4
61 #define AR7_GPIO_DIR 0x8
62 #define AR7_GPIO_ENABLE 0xC
63
64 #define AR7_GPIO_BIT_STATUS_LED 8
65
66 #define AR7_CHIP_7100 0x18
67 #define AR7_CHIP_7200 0x2b
68 #define AR7_CHIP_7300 0x05
69
70 /* Interrupts */
71 #define AR7_IRQ_UART0 15
72 #define AR7_IRQ_UART1 16
73
74 struct plat_cpmac_data {
75 int reset_bit;
76 int power_bit;
77 u32 phy_mask;
78 char dev_addr[6];
79 };
80
81 struct plat_dsl_data {
82 int reset_bit_dsl;
83 int reset_bit_sar;
84 };
85
86 extern char *prom_getenv(char *envname);
87
88 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
89
90 static inline u16 ar7_chip_id(void)
91 {
92 return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
93 }
94
95 static inline u8 ar7_chip_rev(void)
96 {
97 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
98 }
99
100 static inline int ar7_cpu_freq(void)
101 {
102 return ar7_cpu_clock;
103 }
104
105 static inline int ar7_bus_freq(void)
106 {
107 return ar7_bus_clock;
108 }
109
110 static inline int ar7_vbus_freq(void)
111 {
112 return ar7_bus_clock / 2;
113 }
114 #define ar7_cpmac_freq ar7_vbus_freq
115
116 static inline int ar7_dsp_freq(void)
117 {
118 return ar7_dsp_clock;
119 }
120
121 static inline int ar7_has_high_cpmac(void)
122 {
123 u16 chip_id = ar7_chip_id();
124 switch (chip_id) {
125 case AR7_CHIP_7100:
126 case AR7_CHIP_7200:
127 return 0;
128 default:
129 return 1;
130 }
131 }
132 #define ar7_has_high_vlynq ar7_has_high_cpmac
133
134 static inline void ar7_device_enable(u32 bit)
135 {
136 void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
137 writel(readl(reset_reg) | (1 << bit), reset_reg);
138 mdelay(20);
139 }
140
141 static inline void ar7_device_disable(u32 bit)
142 {
143 void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
144 writel(readl(reset_reg) & ~(1 << bit), reset_reg);
145 mdelay(20);
146 }
147
148 static inline void ar7_device_reset(u32 bit)
149 {
150 ar7_device_disable(bit);
151 ar7_device_enable(bit);
152 }
153
154 static inline void ar7_device_on(u32 bit)
155 {
156 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
157 writel(readl(power_reg) | (1 << bit), power_reg);
158 mdelay(20);
159 }
160
161 static inline void ar7_device_off(u32 bit)
162 {
163 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
164 writel(readl(power_reg) & ~(1 << bit), power_reg);
165 mdelay(20);
166 }
167
168 #endif