Fix edimax image generation
[openwrt/svn-archive/archive.git] / target / linux / ar7-2.6 / files / include / asm-mips / ar7 / ar7.h
1 /*
2 * $Id$
3 *
4 * Copyright (C) 2006, 2007 OpenWrt.org
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 #ifndef __AR7_H__
22 #define __AR7_H__
23
24 #include <asm/addrspace.h>
25 #include <linux/delay.h>
26
27 #define AR7_REGS_BASE 0x08610000
28
29 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
30 #define AR7_REGS_EMIF (AR7_REGS_BASE + 0x0800)
31 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
32 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
33 #define AR7_REGS_WDT (AR7_REGS_BASE + 0x0b00)
34 #define AR7_REGS_TIMER0 (AR7_REGS_BASE + 0x0c00)
35 #define AR7_REGS_TIMER1 (AR7_REGS_BASE + 0x0d00)
36 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
37 #define AR7_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
38 #define AR7_REGS_I2C (AR7_REGS_BASE + 0x1000)
39 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
40 #define AR7_REGS_DMA (AR7_REGS_BASE + 0x1400)
41 #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
42 #define AR7_REGS_BIST (AR7_REGS_BASE + 0x1700)
43 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
44 #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1A00)
45 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1C00)
46 #define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1E00)
47 #define AR7_REGS_FSER (AR7_REGS_BASE + 0x2000)
48 #define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
49 #define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
50
51 #define AR7_RESET_PEREPHERIAL 0x0
52 #define AR7_RESET_SOFTWARE 0x4
53 #define AR7_RESET_STATUS 0x8
54
55 #define AR7_RESET_BIT_MDIO 22
56
57 /* GPIO control registers */
58 #define AR7_GPIO_INPUT 0x0
59 #define AR7_GPIO_OUTPUT 0x4
60 #define AR7_GPIO_DIR 0x8
61 #define AR7_GPIO_ENABLE 0xC
62
63 #define AR7_GPIO_BIT_STATUS_LED 8
64
65 #define AR7_CHIP_7100 0x18
66 #define AR7_CHIP_7200 0x2b
67 #define AR7_CHIP_7300 0x05
68
69 /* Interrupts */
70 #define AR7_IRQ_UART0 15
71 #define AR7_IRQ_UART1 16
72
73 struct plat_cpmac_data {
74 int reset_bit;
75 int power_bit;
76 u32 phy_mask;
77 char dev_addr[6];
78 };
79
80 struct plat_dsl_data {
81 int reset_bit_dsl;
82 int reset_bit_sar;
83 };
84
85 extern char *prom_getenv(char *envname);
86
87 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
88
89 static inline u16 ar7_chip_id(void)
90 {
91 return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
92 }
93
94 static inline u8 ar7_chip_rev(void)
95 {
96 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
97 }
98
99 static inline int ar7_cpu_freq(void)
100 {
101 return ar7_cpu_clock;
102 }
103
104 static inline int ar7_bus_freq(void)
105 {
106 return ar7_bus_clock;
107 }
108
109 static inline int ar7_vbus_freq(void)
110 {
111 return ar7_bus_clock / 2;
112 }
113 #define ar7_cpmac_freq ar7_vbus_freq
114
115 static inline int ar7_dsp_freq(void)
116 {
117 return ar7_dsp_clock;
118 }
119
120 static inline int ar7_has_high_cpmac(void)
121 {
122 u16 chip_id = ar7_chip_id();
123 switch (chip_id) {
124 case AR7_CHIP_7100:
125 case AR7_CHIP_7200:
126 return 0;
127 default:
128 return 1;
129 }
130 }
131 #define ar7_has_high_vlynq ar7_has_high_cpmac
132
133 static inline void ar7_device_enable(u32 bit)
134 {
135 void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
136 writel(readl(reset_reg) | (1 << bit), reset_reg);
137 mdelay(20);
138 }
139
140 static inline void ar7_device_disable(u32 bit)
141 {
142 void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
143 writel(readl(reset_reg) & ~(1 << bit), reset_reg);
144 mdelay(20);
145 }
146
147 static inline void ar7_device_reset(u32 bit)
148 {
149 ar7_device_disable(bit);
150 ar7_device_enable(bit);
151 }
152
153 static inline void ar7_device_on(u32 bit)
154 {
155 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
156 writel(readl(power_reg) | (1 << bit), power_reg);
157 mdelay(20);
158 }
159
160 static inline void ar7_device_off(u32 bit)
161 {
162 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
163 writel(readl(power_reg) & ~(1 << bit), power_reg);
164 mdelay(20);
165 }
166
167 #endif