target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h

   1 /*
   2  * $Id$
   3  *
   4  * Copyright (C) 2006, 2007 OpenWrt.org
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #ifndef __AR7_H__
  22 #define __AR7_H__
  23
  24 #include <asm/addrspace.h>
  25 #include <linux/delay.h>
  26
  27 #define AR7_REGS_BASE 0x08610000
  28
  29 #define AR7_REGS_MAC0   (AR7_REGS_BASE + 0x0000)
  30 #define AR7_REGS_EMIF   (AR7_REGS_BASE + 0x0800)
  31 #define AR7_REGS_GPIO   (AR7_REGS_BASE + 0x0900)
  32 #define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00)
  33 #define AR7_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
  34 #define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
  35 #define AR7_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
  36 #define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
  37 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
  38 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1C00)
  39 #define AR7_REGS_MDIO   (AR7_REGS_BASE + 0x1E00)
  40 #define AR7_REGS_IRQ    (AR7_REGS_BASE + 0x2400)
  41 #define AR7_REGS_MAC1   (AR7_REGS_BASE + 0x2800)
  42
  43 #define  AR7_RESET_PEREPHERIAL 0x0
  44 #define  AR7_RESET_SOFTWARE    0x4
  45 #define  AR7_RESET_STATUS      0x8
  46
  47 #define AR7_RESET_BIT_MDIO   22
  48
  49 /* GPIO control registers */
  50 #define  AR7_GPIO_INPUT  0x0
  51 #define  AR7_GPIO_OUTPUT 0x4
  52 #define  AR7_GPIO_DIR    0x8
  53 #define  AR7_GPIO_ENABLE 0xC
  54
  55 #define AR7_GPIO_BIT_STATUS_LED   8
  56
  57
  58 /* Interrupts */
  59 #define AR7_IRQ_UART0  15
  60 #define AR7_IRQ_UART1  16
  61
  62 struct plat_cpmac_data {
  63         int reset_bit;
  64         int power_bit;
  65         u32 phy_mask;
  66         char dev_addr[6];
  67 };
  68
  69 extern char *prom_getenv(char *envname);
  70
  71 /* A bunch of small bit-toggling functions */
  72 static inline u32 get_chip_id(void)
  73 {
  74         return *((u16 *)KSEG1ADDR(AR7_REGS_GPIO + 0x14));
  75 }
  76
  77 static inline int ar7_cpu_freq(void)
  78 {
  79         u16 chip_id = get_chip_id();
  80         switch (chip_id) {
  81         case 0x5:
  82                 return 150000000;
  83         case 0x18:
  84         case 0x2b:
  85                 return 211968000;
  86         default:
  87                 return 150000000;
  88         }
  89 }
  90
  91 static inline int ar7_bus_freq(void)
  92 {
  93         u16 chip_id = get_chip_id();
  94         switch (chip_id) {
  95         case 0x5:
  96                 return 125000000;
  97         case 0x18:
  98         case 0x2b:
  99                 return 105984000;
 100         default:
 101                 return 125000000;
 102         }
 103 }
 104 #define ar7_cpmac_freq ar7_bus_freq
 105
 106 static inline int ar7_has_high_cpmac(void)
 107 {
 108         u16 chip_id = get_chip_id();
 109         switch (chip_id) {
 110         case 0x18:
 111         case 0x2b:
 112                 return 0;
 113         default:
 114                 return 1;
 115         }
 116 }
 117 #define ar7_has_high_vlynq ar7_has_high_cpmac
 118
 119 static inline void ar7_device_enable(u32 bit)
 120 {
 121         volatile u32 *reset_reg = (u32 *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
 122         *reset_reg |= (1 << bit);
 123         mdelay(20);
 124 }
 125
 126 static inline void ar7_device_disable(u32 bit)
 127 {
 128         volatile u32 *reset_reg = (u32 *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
 129         *reset_reg &= ~(1 << bit);
 130         mdelay(20);
 131 }
 132
 133 static inline void ar7_device_reset(u32 bit)
 134 {
 135         ar7_device_disable(bit);
 136         ar7_device_enable(bit);
 137 }
 138
 139 static inline void ar7_device_on(u32 bit)
 140 {
 141         volatile u32 *power_reg = (u32 *)KSEG1ADDR(AR7_REGS_POWER);
 142         *power_reg |= (1 << bit);
 143         mdelay(20);
 144 }
 145
 146 static inline void ar7_device_off(u32 bit)
 147 {
 148         volatile u32 *power_reg = (u32 *)KSEG1ADDR(AR7_REGS_POWER);
 149         *power_reg &= ~(1 << bit);
 150         mdelay(20);
 151 }
 152
 153 #endif