target/linux/ar7-2.6/patches/100-board_support.patch

   1 diff -Nru linux-2.6.19.2/arch/mips/Kconfig linux-ar7/arch/mips/Kconfig
   2 --- linux-2.6.19.2/arch/mips/Kconfig    2006-12-12 02:32:53.000000000 +0700
   3 +++ linux-ar7/arch/mips/Kconfig 2007-01-29 21:52:21.000000000 +0700
   4 @@ -16,6 +16,21 @@
   5         prompt "System type"
   6         default SGI_IP22
   7
   8 +config AR7
   9 +       bool "Texas Instruments AR7"
  10 +       select BOOT_ELF32
  11 +       select DMA_NONCOHERENT
  12 +       select HW_HAS_PCI
  13 +       select IRQ_CPU
  14 +       select SWAP_IO_SPACE
  15 +       select SYS_HAS_CPU_MIPS32_R1
  16 +       select SYS_HAS_EARLY_PRINTK
  17 +       select SYS_SUPPORTS_32BIT_KERNEL
  18 +       select SYS_SUPPORTS_LITTLE_ENDIAN
  19 +       select SYS_SUPPORTS_KGDB
  20 +       select NEED_MULTIPLE_NODES
  21 +       select GENERIC_GPIO
  22 +
  23  config MIPS_MTX1
  24         bool "4G Systems MTX-1 board"
  25         select DMA_NONCOHERENT
  26 diff -Nru linux-2.6.19.2/arch/mips/Makefile linux-ar7/arch/mips/Makefile
  27 --- linux-2.6.19.2/arch/mips/Makefile   2006-12-12 02:32:53.000000000 +0700
  28 +++ linux-ar7/arch/mips/Makefile        2007-01-29 21:52:21.000000000 +0700
  29 @@ -158,6 +158,13 @@
  30  #
  31
  32  #
  33 +# Texas Instruments AR7
  34 +#
  35 +core-$(CONFIG_AR7)             += arch/mips/ar7/
  36 +cflags-$(CONFIG_AR7)           += -Iinclude/asm-mips/ar7
  37 +load-$(CONFIG_AR7)             += 0xffffffff94100000
  38 +
  39 +#
  40  # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
  41  #
  42  core-$(CONFIG_MACH_JAZZ)       += arch/mips/jazz/
  43 diff -Nru linux-2.6.19.2/arch/mips/kernel/setup.c linux-ar7/arch/mips/kernel/setup.c
  44 --- linux-2.6.19.2orig/arch/mips/kernel/setup.c 2006-12-12 02:32:53.000000000 +0700
  45 +++ linux-ar7/arch/mips/kernel/setup.c  2007-03-04 22:32:13.000000000 +0700
  46 @@ -236,7 +236,7 @@
  47   * Initialize the bootmem allocator. It also setup initrd related data
  48   * if needed.
  49   */
  50 -#ifdef CONFIG_SGI_IP27
  51 +#ifdef CONFIG_NEED_MULTIPLE_NODES
  52
  53  static void __init bootmem_init(void)
  54  {
  55 @@ -244,7 +244,7 @@
  56         finalize_initrd();
  57  }
  58
  59 -#else  /* !CONFIG_SGI_IP27 */
  60 +#else  /* !CONFIG_NEED_MULTIPLE_NODES */
  61
  62  static void __init bootmem_init(void)
  63  {
  64 @@ -349,7 +349,7 @@
  65         finalize_initrd();
  66  }
  67
  68 -#endif /* CONFIG_SGI_IP27 */
  69 +#endif /* CONFIG_NEED_MULTIPLE_NODES */
  70
  71  /*
  72   * arch_mem_init - initialize memory managment subsystem
  73 diff -Nru linux-2.6.19.2/arch/mips/kernel/traps.c linux-ar7/arch/mips/kernel/traps.c
  74 --- linux-2.6.19.2/arch/mips/kernel/traps.c     2007-01-11 02:10:37.000000000 +0700
  75 +++ linux-ar7/arch/mips/kernel/traps.c  2007-03-15 13:19:19.000000000 +0700
  76 @@ -1072,11 +1072,6 @@
  77  unsigned long exception_handlers[32];
  78  unsigned long vi_handlers[64];
  79
  80 -/*
  81 - * As a side effect of the way this is implemented we're limited
  82 - * to interrupt handlers in the address range from
  83 - * KSEG0 <= x < KSEG0 + 256mb on the Nevada.  Oh well ...
  84 - */
  85  void *set_except_vector(int n, void *addr)
  86  {
  87         unsigned long handler = (unsigned long) addr;
  88 @@ -1084,9 +1079,15 @@
  89
  90         exception_handlers[n] = handler;
  91         if (n == 0 && cpu_has_divec) {
  92 -               *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
  93 -                                                (0x03ffffff & (handler >> 2));
  94 -               flush_icache_range(ebase + 0x200, ebase + 0x204);
  95 +               /* lui k0, 0x0000 */
  96 +               *(volatile u32 *)(CAC_BASE+0x200) = 0x3c1a0000 | (handler >> 16);
  97 +               /* ori k0, 0x0000 */
  98 +               *(volatile u32 *)(CAC_BASE+0x204) = 0x375a0000 | (handler & 0xffff);
  99 +               /* jr k0 */
 100 +               *(volatile u32 *)(CAC_BASE+0x208) = 0x03400008;
 101 +               /* nop */
 102 +               *(volatile u32 *)(CAC_BASE+0x20C) = 0x00000000;
 103 +               flush_icache_range(CAC_BASE+0x200, CAC_BASE+0x210);
 104         }
 105         return (void *)old_handler;
 106  }