target/linux/ar7/files/arch/mips/ar7/clock.c

   1 /*
   2  * Copyright (C) 2007 OpenWrt.org
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/types.h>
  21 #include <linux/module.h>
  22 #include <linux/delay.h>
  23 #include <asm/addrspace.h>
  24 #include <asm/io.h>
  25 #include <asm/ar7/ar7.h>
  26
  27 #define BOOT_PLL_SOURCE_MASK 0x3
  28 #define CPU_PLL_SOURCE_SHIFT 16
  29 #define BUS_PLL_SOURCE_SHIFT 14
  30 #define USB_PLL_SOURCE_SHIFT 18
  31 #define DSP_PLL_SOURCE_SHIFT 22
  32 #define BOOT_PLL_SOURCE_AFE 0
  33 #define BOOT_PLL_SOURCE_BUS 0
  34 #define BOOT_PLL_SOURCE_REF 1
  35 #define BOOT_PLL_SOURCE_XTAL 2
  36 #define BOOT_PLL_SOURCE_CPU 3
  37 #define BOOT_PLL_BYPASS 0x00000020
  38 #define BOOT_PLL_ASYNC_MODE 0x02000000
  39 #define BOOT_PLL_2TO1_MODE 0x00008000
  40
  41 #define TNETD7200_CLOCK_ID_CPU 0
  42 #define TNETD7200_CLOCK_ID_DSP 1
  43 #define TNETD7200_CLOCK_ID_USB 2
  44
  45 #define TNETD7200_DEF_CPU_CLK 211000000
  46 #define TNETD7200_DEF_DSP_CLK 125000000
  47 #define TNETD7200_DEF_USB_CLK 48000000
  48
  49 struct tnetd7300_clock {
  50         volatile u32 ctrl;
  51 #define PREDIV_MASK 0x001f0000
  52 #define PREDIV_SHIFT 16
  53 #define POSTDIV_MASK 0x0000001f
  54         u32 unused1[3];
  55         volatile u32 pll;
  56 #define MUL_MASK 0x0000f000
  57 #define MUL_SHIFT 12
  58 #define PLL_MODE_MASK 0x00000001
  59 #define PLL_NDIV 0x00000800
  60 #define PLL_DIV 0x00000002
  61 #define PLL_STATUS 0x00000001
  62         u32 unused2[3];
  63 } __attribute__ ((packed));
  64
  65 struct tnetd7300_clocks {
  66         struct tnetd7300_clock bus;
  67         struct tnetd7300_clock cpu;
  68         struct tnetd7300_clock usb;
  69         struct tnetd7300_clock dsp;
  70 } __attribute__ ((packed));
  71
  72 struct tnetd7200_clock {
  73         volatile u32 ctrl;
  74         u32 unused1[3];
  75 #define DIVISOR_ENABLE_MASK 0x00008000
  76         volatile u32 mul;
  77         volatile u32 prediv;
  78         volatile u32 postdiv;
  79         volatile u32 postdiv2;
  80         u32 unused2[6];
  81         volatile u32 cmd;
  82         volatile u32 status;
  83         volatile u32 cmden;
  84         u32 padding[15];
  85 } __attribute__ ((packed));
  86
  87 struct tnetd7200_clocks {
  88         struct tnetd7200_clock cpu;
  89         struct tnetd7200_clock dsp;
  90         struct tnetd7200_clock usb;
  91 } __attribute__ ((packed));
  92
  93 int ar7_cpu_clock = 150000000;
  94 EXPORT_SYMBOL(ar7_cpu_clock);
  95 int ar7_bus_clock = 125000000;
  96 EXPORT_SYMBOL(ar7_bus_clock);
  97 int ar7_dsp_clock;
  98 EXPORT_SYMBOL(ar7_dsp_clock);
  99
 100 static int gcd(int a, int b)
 101 {
 102         int c;
 103
 104         if (a < b) {
 105                 c = a;
 106                 a = b;
 107                 b = c;
 108         }
 109         while ((c = (a % b))) {
 110                 a = b;
 111                 b = c;
 112         }
 113         return b;
 114 }
 115
 116 static void approximate(int base, int target, int *prediv,
 117                         int *postdiv, int *mul)
 118 {
 119         int i, j, k, freq, res = target;
 120         for (i = 1; i <= 16; i++) {
 121                 for (j = 1; j <= 32; j++) {
 122                         for (k = 1; k <= 32; k++) {
 123                                 freq = abs(base / j * i / k - target);
 124                                 if (freq < res) {
 125                                         res = freq;
 126                                         *mul = i;
 127                                         *prediv = j;
 128                                         *postdiv = k;
 129                                 }
 130                         }
 131                 }
 132         }
 133 }
 134
 135 static void calculate(int base, int target, int *prediv, int *postdiv,
 136         int *mul)
 137 {
 138         int tmp_gcd, tmp_base, tmp_freq;
 139
 140         for (*prediv = 1; *prediv <= 32; (*prediv)++) {
 141                 tmp_base = base / *prediv;
 142                 tmp_gcd = gcd(target, tmp_base);
 143                 *mul = target / tmp_gcd;
 144                 *postdiv = tmp_base / tmp_gcd;
 145                 if ((*mul < 1) || (*mul >= 16))
 146                         continue;
 147                 if ((*postdiv > 0) & (*postdiv <= 32))
 148                         break;
 149         }
 150
 151         if (base / (*prediv) * (*mul) / (*postdiv) != target) {
 152                 approximate(base, target, prediv, postdiv, mul);
 153                 tmp_freq = base / (*prediv) * (*mul) / (*postdiv);
 154                 printk(KERN_WARNING
 155                        "Adjusted requested frequency %d to %d\n",
 156                        target, tmp_freq);
 157         }
 158
 159         printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
 160                *prediv, *postdiv, *mul);
 161 }
 162
 163 static int tnetd7300_dsp_clock(void)
 164 {
 165         u32 didr1, didr2;
 166         u8 rev = ar7_chip_rev();
 167         didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
 168         didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
 169         if (didr2 & (1 << 23))
 170                 return 0;
 171         if ((rev >= 0x23) && (rev != 0x57))
 172                 return 250000000;
 173         if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
 174             > 4208000)
 175                 return 250000000;
 176         return 0;
 177 }
 178
 179 static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
 180         u32 *bootcr, u32 bus_clock)
 181 {
 182         int product;
 183         int base_clock = AR7_REF_CLOCK;
 184         u32 ctrl = clock->ctrl;
 185         u32 pll = clock->pll;
 186         int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
 187         int postdiv = (ctrl & POSTDIV_MASK) + 1;
 188         int divisor = prediv * postdiv;
 189         int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
 190
 191         switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
 192         case BOOT_PLL_SOURCE_BUS:
 193                 base_clock = bus_clock;
 194                 break;
 195         case BOOT_PLL_SOURCE_REF:
 196                 base_clock = AR7_REF_CLOCK;
 197                 break;
 198         case BOOT_PLL_SOURCE_XTAL:
 199                 base_clock = AR7_XTAL_CLOCK;
 200                 break;
 201         case BOOT_PLL_SOURCE_CPU:
 202                 base_clock = ar7_cpu_clock;
 203                 break;
 204         }
 205
 206         if (*bootcr & BOOT_PLL_BYPASS)
 207                 return base_clock / divisor;
 208
 209         if ((pll & PLL_MODE_MASK) == 0)
 210                 return (base_clock >> (mul / 16 + 1)) / divisor;
 211
 212         if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
 213                 product = (mul & 1) ?
 214                         (base_clock * mul) >> 1 :
 215                         (base_clock * (mul - 1)) >> 2;
 216                 return product / divisor;
 217         }
 218
 219         if (mul == 16)
 220                 return base_clock / divisor;
 221
 222         return base_clock * mul / divisor;
 223 }
 224
 225 static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
 226         u32 *bootcr, u32 frequency)
 227 {
 228         u32 status;
 229         int prediv, postdiv, mul;
 230         int base_clock = ar7_bus_clock;
 231
 232         switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
 233         case BOOT_PLL_SOURCE_BUS:
 234                 base_clock = ar7_bus_clock;
 235                 break;
 236         case BOOT_PLL_SOURCE_REF:
 237                 base_clock = AR7_REF_CLOCK;
 238                 break;
 239         case BOOT_PLL_SOURCE_XTAL:
 240                 base_clock = AR7_XTAL_CLOCK;
 241                 break;
 242         case BOOT_PLL_SOURCE_CPU:
 243                 base_clock = ar7_cpu_clock;
 244                 break;
 245         }
 246
 247         calculate(base_clock, frequency, &prediv, &postdiv, &mul);
 248
 249         clock->ctrl = ((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1);
 250         mdelay(1);
 251         clock->pll = 4;
 252         do {
 253                 status = clock->pll;
 254         } while (status & PLL_STATUS);
 255         clock->pll = ((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e;
 256         mdelay(75);
 257 }
 258
 259 static void __init tnetd7300_init_clocks(void)
 260 {
 261         u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
 262         struct tnetd7300_clocks *clocks =
 263                                         (struct tnetd7300_clocks *)
 264                                         ioremap_nocache(AR7_REGS_POWER + 0x20,
 265                                         sizeof(struct tnetd7300_clocks));
 266
 267         ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
 268                 &clocks->bus, bootcr, AR7_AFE_CLOCK);
 269
 270         if (*bootcr & BOOT_PLL_ASYNC_MODE) {
 271                 ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
 272                         &clocks->cpu, bootcr, AR7_AFE_CLOCK);
 273         } else {
 274                 ar7_cpu_clock = ar7_bus_clock;
 275         }
 276 /*
 277         tnetd7300_set_clock(USB_PLL_SOURCE_SHIFT, &clocks->usb,
 278                 bootcr, 48000000);
 279 */
 280         if (ar7_dsp_clock == 250000000)
 281                 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
 282                         bootcr, ar7_dsp_clock);
 283
 284         iounmap(clocks);
 285         iounmap(bootcr);
 286 }
 287
 288 static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
 289         u32 *bootcr, u32 bus_clock)
 290 {
 291         int divisor = ((clock->prediv & 0x1f) + 1) *
 292                 ((clock->postdiv & 0x1f) + 1);
 293
 294         if (*bootcr & BOOT_PLL_BYPASS)
 295                 return base / divisor;
 296
 297         return base * ((clock->mul & 0xf) + 1) / divisor;
 298 }
 299
 300
 301 static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
 302         int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
 303 {
 304         printk(KERN_INFO
 305                 "Clocks: base = %d, frequency = %u, prediv = %d, "
 306                 "postdiv = %d, postdiv2 = %d, mul = %d\n",
 307                 base, frequency, prediv, postdiv, postdiv2, mul);
 308
 309         clock->ctrl = 0;
 310         clock->prediv = DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F);
 311         clock->mul = ((mul - 1) & 0xF);
 312
 313         for (mul = 0; mul < 2000; mul++) /* nop */;
 314
 315         while (clock->status & 0x1) /* nop */;
 316
 317         clock->postdiv = DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F);
 318
 319         clock->cmden |= 1;
 320         clock->cmd |= 1;
 321
 322         while (clock->status & 0x1) /* nop */;
 323
 324         clock->postdiv2 = DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F);
 325
 326         clock->cmden |= 1;
 327         clock->cmd |= 1;
 328
 329         while (clock->status & 0x1) /* nop */;
 330
 331         clock->ctrl |= 1;
 332 }
 333
 334 static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
 335 {
 336         if (*bootcr & BOOT_PLL_ASYNC_MODE) {
 337                 /* Async */
 338                 switch (clock_id) {
 339                 case TNETD7200_CLOCK_ID_DSP:
 340                         return AR7_REF_CLOCK;
 341                 default:
 342                         return AR7_AFE_CLOCK;
 343                 }
 344         } else {
 345                 /* Sync */
 346                 if (*bootcr & BOOT_PLL_2TO1_MODE) {
 347                         /* 2:1 */
 348                         switch (clock_id) {
 349                         case TNETD7200_CLOCK_ID_DSP:
 350                                 return AR7_REF_CLOCK;
 351                         default:
 352                                 return AR7_AFE_CLOCK;
 353                         }
 354                 } else {
 355                         /* 1:1 */
 356                         return AR7_REF_CLOCK;
 357                 }
 358         }
 359 }
 360
 361
 362 static void __init tnetd7200_init_clocks(void)
 363 {
 364         u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
 365         struct tnetd7200_clocks *clocks =
 366                                         (struct tnetd7200_clocks *)
 367                                         ioremap_nocache(AR7_REGS_POWER + 0x80,
 368                                         sizeof(struct tnetd7200_clocks));
 369         int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
 370         int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
 371         int usb_base, usb_mul, usb_prediv, usb_postdiv;
 372
 373 /*
 374         Log from Fritz!Box 7170 Annex B:
 375
 376         CPU revision is: 00018448
 377         Clocks: Async mode
 378         Clocks: Setting DSP clock
 379         Clocks: prediv: 1, postdiv: 1, mul: 5
 380         Clocks: base = 25000000, frequency = 125000000, prediv = 1,
 381                         postdiv = 2, postdiv2 = 1, mul = 10
 382         Clocks: Setting CPU clock
 383         Adjusted requested frequency 211000000 to 211968000
 384         Clocks: prediv: 1, postdiv: 1, mul: 6
 385         Clocks: base = 35328000, frequency = 211968000, prediv = 1,
 386                         postdiv = 1, postdiv2 = -1, mul = 6
 387         Clocks: Setting USB clock
 388         Adjusted requested frequency 48000000 to 48076920
 389         Clocks: prediv: 13, postdiv: 1, mul: 5
 390         Clocks: base = 125000000, frequency = 48000000, prediv = 13,
 391                         postdiv = 1, postdiv2 = -1, mul = 5
 392
 393         DSL didn't work if you didn't set the postdiv 2:1 postdiv2 combination,
 394         driver hung on startup.
 395         Haven't tested this on a synchronous board,
 396         neither do i know what to do with ar7_dsp_clock
 397 */
 398
 399         cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
 400         dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
 401
 402         if (*bootcr & BOOT_PLL_ASYNC_MODE) {
 403                 printk(KERN_INFO "Clocks: Async mode\n");
 404
 405                 printk(KERN_INFO "Clocks: Setting DSP clock\n");
 406                 calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
 407                         &dsp_prediv, &dsp_postdiv, &dsp_mul);
 408                 ar7_bus_clock =
 409                         ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
 410                 tnetd7200_set_clock(dsp_base, &clocks->dsp,
 411                         dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
 412                         ar7_bus_clock);
 413
 414                 printk(KERN_INFO "Clocks: Setting CPU clock\n");
 415                 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
 416                         &cpu_postdiv, &cpu_mul);
 417                 ar7_cpu_clock =
 418                         ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
 419                 tnetd7200_set_clock(cpu_base, &clocks->cpu,
 420                         cpu_prediv, cpu_postdiv, -1, cpu_mul,
 421                         ar7_cpu_clock);
 422
 423         } else {
 424                 if (*bootcr & BOOT_PLL_2TO1_MODE) {
 425                         printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
 426
 427                         printk(KERN_INFO "Clocks: Setting CPU clock\n");
 428                         calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
 429                                 &cpu_postdiv, &cpu_mul);
 430                         ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul)
 431                                                                 / cpu_postdiv;
 432                         tnetd7200_set_clock(cpu_base, &clocks->cpu,
 433                                 cpu_prediv, cpu_postdiv, -1, cpu_mul,
 434                                 ar7_cpu_clock);
 435
 436                         printk(KERN_INFO "Clocks: Setting DSP clock\n");
 437                         calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
 438                                 &dsp_postdiv, &dsp_mul);
 439                         ar7_bus_clock = ar7_cpu_clock / 2;
 440                         tnetd7200_set_clock(dsp_base, &clocks->dsp,
 441                                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
 442                                 dsp_mul * 2, ar7_bus_clock);
 443                 } else {
 444                         printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
 445
 446                         printk(KERN_INFO "Clocks: Setting DSP clock\n");
 447                         calculate(dsp_base, TNETD7200_DEF_CPU_CLK, &dsp_prediv,
 448                                 &dsp_postdiv, &dsp_mul);
 449                         ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul)
 450                                                                 / dsp_postdiv;
 451                         tnetd7200_set_clock(dsp_base, &clocks->dsp,
 452                                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
 453                                 dsp_mul * 2, ar7_bus_clock);
 454
 455                         ar7_cpu_clock = ar7_bus_clock;
 456                 }
 457         }
 458
 459         printk(KERN_INFO "Clocks: Setting USB clock\n");
 460         usb_base = ar7_bus_clock;
 461         calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
 462                 &usb_postdiv, &usb_mul);
 463         tnetd7200_set_clock(usb_base, &clocks->usb,
 464                 usb_prediv, usb_postdiv, -1, usb_mul,
 465                 TNETD7200_DEF_USB_CLK);
 466
 467         #warning FIXME
 468         ar7_dsp_clock = ar7_cpu_clock;
 469
 470         iounmap(clocks);
 471         iounmap(bootcr);
 472 }
 473
 474 void __init ar7_init_clocks(void)
 475 {
 476         switch (ar7_chip_id()) {
 477         case AR7_CHIP_7100:
 478 #warning FIXME: Check if the new 7200 clock init works for 7100
 479                 tnetd7200_init_clocks();
 480                 break;
 481         case AR7_CHIP_7200:
 482                 tnetd7200_init_clocks();
 483                 break;
 484         case AR7_CHIP_7300:
 485                 ar7_dsp_clock = tnetd7300_dsp_clock();
 486                 tnetd7300_init_clocks();
 487                 break;
 488         default:
 489                 break;
 490         }
 491 }