target/linux/ar7/files/arch/mips/ar7/clock.c

   1 /*
   2  * Copyright (C) 2007 OpenWrt.org
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/types.h>
  21 #include <linux/module.h>
  22 #include <linux/delay.h>
  23 #include <asm/addrspace.h>
  24 #include <asm/io.h>
  25 #include <asm/ar7/ar7.h>
  26
  27 #define BOOT_PLL_SOURCE_MASK    0x3
  28 #define CPU_PLL_SOURCE_SHIFT    16
  29 #define BUS_PLL_SOURCE_SHIFT    14
  30 #define USB_PLL_SOURCE_SHIFT    18
  31 #define DSP_PLL_SOURCE_SHIFT    22
  32 #define BOOT_PLL_SOURCE_AFE     0
  33 #define BOOT_PLL_SOURCE_BUS     0
  34 #define BOOT_PLL_SOURCE_REF     1
  35 #define BOOT_PLL_SOURCE_XTAL    2
  36 #define BOOT_PLL_SOURCE_CPU     3
  37 #define BOOT_PLL_BYPASS         0x00000020
  38 #define BOOT_PLL_ASYNC_MODE     0x02000000
  39 #define BOOT_PLL_2TO1_MODE      0x00008000
  40
  41 #define TNETD7200_CLOCK_ID_CPU  0
  42 #define TNETD7200_CLOCK_ID_DSP  1
  43 #define TNETD7200_CLOCK_ID_USB  2
  44
  45 #define TNETD7200_DEF_CPU_CLK   211000000
  46 #define TNETD7200_DEF_DSP_CLK   125000000
  47 #define TNETD7200_DEF_USB_CLK   48000000
  48
  49 struct tnetd7300_clock {
  50         volatile u32 ctrl;
  51 #define PREDIV_MASK     0x001f0000
  52 #define PREDIV_SHIFT    16
  53 #define POSTDIV_MASK    0x0000001f
  54         u32 unused1[3];
  55         volatile u32 pll;
  56 #define MUL_MASK        0x0000f000
  57 #define MUL_SHIFT       12
  58 #define PLL_MODE_MASK   0x00000001
  59 #define PLL_NDIV        0x00000800
  60 #define PLL_DIV         0x00000002
  61 #define PLL_STATUS      0x00000001
  62         u32 unused2[3];
  63 } __packed;
  64
  65 struct tnetd7300_clocks {
  66         struct tnetd7300_clock bus;
  67         struct tnetd7300_clock cpu;
  68         struct tnetd7300_clock usb;
  69         struct tnetd7300_clock dsp;
  70 } __packed;
  71
  72 struct tnetd7200_clock {
  73         volatile u32 ctrl;
  74         u32 unused1[3];
  75 #define DIVISOR_ENABLE_MASK 0x00008000
  76         volatile u32 mul;
  77         volatile u32 prediv;
  78         volatile u32 postdiv;
  79         volatile u32 postdiv2;
  80         u32 unused2[6];
  81         volatile u32 cmd;
  82         volatile u32 status;
  83         volatile u32 cmden;
  84         u32 padding[15];
  85 } __packed;
  86
  87 struct tnetd7200_clocks {
  88         struct tnetd7200_clock cpu;
  89         struct tnetd7200_clock dsp;
  90         struct tnetd7200_clock usb;
  91 } __packed;
  92
  93 int ar7_cpu_clock = 150000000;
  94 EXPORT_SYMBOL(ar7_cpu_clock);
  95 int ar7_bus_clock = 125000000;
  96 EXPORT_SYMBOL(ar7_bus_clock);
  97 int ar7_dsp_clock;
  98 EXPORT_SYMBOL(ar7_dsp_clock);
  99
 100 static int gcd(int a, int b)
 101 {
 102         int c;
 103
 104         if (a < b) {
 105                 c = a;
 106                 a = b;
 107                 b = c;
 108         }
 109         while ((c = (a % b))) {
 110                 a = b;
 111                 b = c;
 112         }
 113         return b;
 114 }
 115
 116 static void approximate(int base, int target, int *prediv,
 117                         int *postdiv, int *mul)
 118 {
 119         int i, j, k, freq, res = target;
 120         for (i = 1; i <= 16; i++)
 121                 for (j = 1; j <= 32; j++)
 122                         for (k = 1; k <= 32; k++) {
 123                                 freq = abs(base / j * i / k - target);
 124                                 if (freq < res) {
 125                                         res = freq;
 126                                         *mul = i;
 127                                         *prediv = j;
 128                                         *postdiv = k;
 129                                 }
 130                         }
 131 }
 132
 133 static void calculate(int base, int target, int *prediv, int *postdiv,
 134         int *mul)
 135 {
 136         int tmp_gcd, tmp_base, tmp_freq;
 137
 138         for (*prediv = 1; *prediv <= 32; (*prediv)++) {
 139                 tmp_base = base / *prediv;
 140                 tmp_gcd = gcd(target, tmp_base);
 141                 *mul = target / tmp_gcd;
 142                 *postdiv = tmp_base / tmp_gcd;
 143                 if ((*mul < 1) || (*mul >= 16))
 144                         continue;
 145                 if ((*postdiv > 0) & (*postdiv <= 32))
 146                         break;
 147         }
 148
 149         if (base / (*prediv) * (*mul) / (*postdiv) != target) {
 150                 approximate(base, target, prediv, postdiv, mul);
 151                 tmp_freq = base / (*prediv) * (*mul) / (*postdiv);
 152                 printk(KERN_WARNING
 153                        "Adjusted requested frequency %d to %d\n",
 154                        target, tmp_freq);
 155         }
 156
 157         printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
 158                *prediv, *postdiv, *mul);
 159 }
 160
 161 static int tnetd7300_dsp_clock(void)
 162 {
 163         u32 didr1, didr2;
 164         u8 rev = ar7_chip_rev();
 165         didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
 166         didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
 167         if (didr2 & (1 << 23))
 168                 return 0;
 169         if ((rev >= 0x23) && (rev != 0x57))
 170                 return 250000000;
 171         if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
 172             > 4208000)
 173                 return 250000000;
 174         return 0;
 175 }
 176
 177 static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
 178         u32 *bootcr, u32 bus_clock)
 179 {
 180         int product;
 181         int base_clock = AR7_REF_CLOCK;
 182         u32 ctrl = clock->ctrl;
 183         u32 pll = clock->pll;
 184         int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
 185         int postdiv = (ctrl & POSTDIV_MASK) + 1;
 186         int divisor = prediv * postdiv;
 187         int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
 188
 189         switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
 190         case BOOT_PLL_SOURCE_BUS:
 191                 base_clock = bus_clock;
 192                 break;
 193         case BOOT_PLL_SOURCE_REF:
 194                 base_clock = AR7_REF_CLOCK;
 195                 break;
 196         case BOOT_PLL_SOURCE_XTAL:
 197                 base_clock = AR7_XTAL_CLOCK;
 198                 break;
 199         case BOOT_PLL_SOURCE_CPU:
 200                 base_clock = ar7_cpu_clock;
 201                 break;
 202         }
 203
 204         if (*bootcr & BOOT_PLL_BYPASS)
 205                 return base_clock / divisor;
 206
 207         if ((pll & PLL_MODE_MASK) == 0)
 208                 return (base_clock >> (mul / 16 + 1)) / divisor;
 209
 210         if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
 211                 product = (mul & 1) ?
 212                         (base_clock * mul) >> 1 :
 213                         (base_clock * (mul - 1)) >> 2;
 214                 return product / divisor;
 215         }
 216
 217         if (mul == 16)
 218                 return base_clock / divisor;
 219
 220         return base_clock * mul / divisor;
 221 }
 222
 223 static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
 224         u32 *bootcr, u32 frequency)
 225 {
 226         u32 status;
 227         int prediv, postdiv, mul;
 228         int base_clock = ar7_bus_clock;
 229
 230         switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
 231         case BOOT_PLL_SOURCE_BUS:
 232                 base_clock = ar7_bus_clock;
 233                 break;
 234         case BOOT_PLL_SOURCE_REF:
 235                 base_clock = AR7_REF_CLOCK;
 236                 break;
 237         case BOOT_PLL_SOURCE_XTAL:
 238                 base_clock = AR7_XTAL_CLOCK;
 239                 break;
 240         case BOOT_PLL_SOURCE_CPU:
 241                 base_clock = ar7_cpu_clock;
 242                 break;
 243         }
 244
 245         calculate(base_clock, frequency, &prediv, &postdiv, &mul);
 246
 247         clock->ctrl = ((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1);
 248         mdelay(1);
 249         clock->pll = 4;
 250         do
 251                 status = clock->pll;
 252         while (status & PLL_STATUS);
 253         clock->pll = ((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e;
 254         mdelay(75);
 255 }
 256
 257 static void __init tnetd7300_init_clocks(void)
 258 {
 259         u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
 260         struct tnetd7300_clocks *clocks =
 261                                         (struct tnetd7300_clocks *)
 262                                         ioremap_nocache(AR7_REGS_POWER + 0x20,
 263                                         sizeof(struct tnetd7300_clocks));
 264
 265         ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
 266                 &clocks->bus, bootcr, AR7_AFE_CLOCK);
 267
 268         if (*bootcr & BOOT_PLL_ASYNC_MODE)
 269                 ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
 270                         &clocks->cpu, bootcr, AR7_AFE_CLOCK);
 271         else
 272                 ar7_cpu_clock = ar7_bus_clock;
 273 /*
 274         tnetd7300_set_clock(USB_PLL_SOURCE_SHIFT, &clocks->usb,
 275                 bootcr, 48000000);
 276 */
 277         if (ar7_dsp_clock == 250000000)
 278                 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
 279                         bootcr, ar7_dsp_clock);
 280
 281         iounmap(clocks);
 282         iounmap(bootcr);
 283 }
 284
 285 static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
 286         u32 *bootcr, u32 bus_clock)
 287 {
 288         int divisor = ((clock->prediv & 0x1f) + 1) *
 289                 ((clock->postdiv & 0x1f) + 1);
 290
 291         if (*bootcr & BOOT_PLL_BYPASS)
 292                 return base / divisor;
 293
 294         return base * ((clock->mul & 0xf) + 1) / divisor;
 295 }
 296
 297
 298 static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
 299         int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
 300 {
 301         printk(KERN_INFO
 302                 "Clocks: base = %d, frequency = %u, prediv = %d, "
 303                 "postdiv = %d, postdiv2 = %d, mul = %d\n",
 304                 base, frequency, prediv, postdiv, postdiv2, mul);
 305
 306         clock->ctrl = 0;
 307         clock->prediv = DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F);
 308         clock->mul = ((mul - 1) & 0xF);
 309
 310         for (mul = 0; mul < 2000; mul++) /* nop */;
 311
 312         while (clock->status & 0x1) /* nop */;
 313
 314         clock->postdiv = DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F);
 315
 316         clock->cmden |= 1;
 317         clock->cmd |= 1;
 318
 319         while (clock->status & 0x1) /* nop */;
 320
 321         clock->postdiv2 = DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F);
 322
 323         clock->cmden |= 1;
 324         clock->cmd |= 1;
 325
 326         while (clock->status & 0x1) /* nop */;
 327
 328         clock->ctrl |= 1;
 329 }
 330
 331 static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
 332 {
 333         if (*bootcr & BOOT_PLL_ASYNC_MODE)
 334                 /* Async */
 335                 switch (clock_id) {
 336                 case TNETD7200_CLOCK_ID_DSP:
 337                         return AR7_REF_CLOCK;
 338                 default:
 339                         return AR7_AFE_CLOCK;
 340                 }
 341         else
 342                 /* Sync */
 343                 if (*bootcr & BOOT_PLL_2TO1_MODE)
 344                         /* 2:1 */
 345                         switch (clock_id) {
 346                         case TNETD7200_CLOCK_ID_DSP:
 347                                 return AR7_REF_CLOCK;
 348                         default:
 349                                 return AR7_AFE_CLOCK;
 350                         }
 351                 else
 352                         /* 1:1 */
 353                         return AR7_REF_CLOCK;
 354 }
 355
 356
 357 static void __init tnetd7200_init_clocks(void)
 358 {
 359         u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
 360         struct tnetd7200_clocks *clocks =
 361                                         (struct tnetd7200_clocks *)
 362                                         ioremap_nocache(AR7_REGS_POWER + 0x80,
 363                                         sizeof(struct tnetd7200_clocks));
 364         int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
 365         int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
 366         int usb_base, usb_mul, usb_prediv, usb_postdiv;
 367
 368 /*
 369         Log from Fritz!Box 7170 Annex B:
 370
 371         CPU revision is: 00018448
 372         Clocks: Async mode
 373         Clocks: Setting DSP clock
 374         Clocks: prediv: 1, postdiv: 1, mul: 5
 375         Clocks: base = 25000000, frequency = 125000000, prediv = 1,
 376                         postdiv = 2, postdiv2 = 1, mul = 10
 377         Clocks: Setting CPU clock
 378         Adjusted requested frequency 211000000 to 211968000
 379         Clocks: prediv: 1, postdiv: 1, mul: 6
 380         Clocks: base = 35328000, frequency = 211968000, prediv = 1,
 381                         postdiv = 1, postdiv2 = -1, mul = 6
 382         Clocks: Setting USB clock
 383         Adjusted requested frequency 48000000 to 48076920
 384         Clocks: prediv: 13, postdiv: 1, mul: 5
 385         Clocks: base = 125000000, frequency = 48000000, prediv = 13,
 386                         postdiv = 1, postdiv2 = -1, mul = 5
 387
 388         DSL didn't work if you didn't set the postdiv 2:1 postdiv2 combination,
 389         driver hung on startup.
 390         Haven't tested this on a synchronous board,
 391         neither do i know what to do with ar7_dsp_clock
 392 */
 393
 394         cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
 395         dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
 396
 397         if (*bootcr & BOOT_PLL_ASYNC_MODE) {
 398                 printk(KERN_INFO "Clocks: Async mode\n");
 399
 400                 printk(KERN_INFO "Clocks: Setting DSP clock\n");
 401                 calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
 402                         &dsp_prediv, &dsp_postdiv, &dsp_mul);
 403                 ar7_bus_clock =
 404                         ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
 405                 tnetd7200_set_clock(dsp_base, &clocks->dsp,
 406                         dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
 407                         ar7_bus_clock);
 408
 409                 printk(KERN_INFO "Clocks: Setting CPU clock\n");
 410                 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
 411                         &cpu_postdiv, &cpu_mul);
 412                 ar7_cpu_clock =
 413                         ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
 414                 tnetd7200_set_clock(cpu_base, &clocks->cpu,
 415                         cpu_prediv, cpu_postdiv, -1, cpu_mul,
 416                         ar7_cpu_clock);
 417
 418         } else
 419                 if (*bootcr & BOOT_PLL_2TO1_MODE) {
 420                         printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
 421
 422                         printk(KERN_INFO "Clocks: Setting CPU clock\n");
 423                         calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
 424                                 &cpu_postdiv, &cpu_mul);
 425                         ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul)
 426                                                                 / cpu_postdiv;
 427                         tnetd7200_set_clock(cpu_base, &clocks->cpu,
 428                                 cpu_prediv, cpu_postdiv, -1, cpu_mul,
 429                                 ar7_cpu_clock);
 430
 431                         printk(KERN_INFO "Clocks: Setting DSP clock\n");
 432                         calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
 433                                 &dsp_postdiv, &dsp_mul);
 434                         ar7_bus_clock = ar7_cpu_clock / 2;
 435                         tnetd7200_set_clock(dsp_base, &clocks->dsp,
 436                                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
 437                                 dsp_mul * 2, ar7_bus_clock);
 438                 } else {
 439                         printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
 440
 441                         printk(KERN_INFO "Clocks: Setting DSP clock\n");
 442                         calculate(dsp_base, TNETD7200_DEF_CPU_CLK, &dsp_prediv,
 443                                 &dsp_postdiv, &dsp_mul);
 444                         ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul)
 445                                                                 / dsp_postdiv;
 446                         tnetd7200_set_clock(dsp_base, &clocks->dsp,
 447                                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
 448                                 dsp_mul * 2, ar7_bus_clock);
 449
 450                         ar7_cpu_clock = ar7_bus_clock;
 451                 }
 452
 453         printk(KERN_INFO "Clocks: Setting USB clock\n");
 454         usb_base = ar7_bus_clock;
 455         calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
 456                 &usb_postdiv, &usb_mul);
 457         tnetd7200_set_clock(usb_base, &clocks->usb,
 458                 usb_prediv, usb_postdiv, -1, usb_mul,
 459                 TNETD7200_DEF_USB_CLK);
 460
 461         #warning FIXME
 462         ar7_dsp_clock = ar7_cpu_clock;
 463
 464         iounmap(clocks);
 465         iounmap(bootcr);
 466 }
 467
 468 void __init ar7_init_clocks(void)
 469 {
 470         switch (ar7_chip_id()) {
 471         case AR7_CHIP_7100:
 472 #warning FIXME: Check if the new 7200 clock init works for 7100
 473                 tnetd7200_init_clocks();
 474                 break;
 475         case AR7_CHIP_7200:
 476                 tnetd7200_init_clocks();
 477                 break;
 478         case AR7_CHIP_7300:
 479                 ar7_dsp_clock = tnetd7300_dsp_clock();
 480                 tnetd7300_init_clocks();
 481                 break;
 482         default:
 483                 break;
 484         }
 485 }