AR7: IRQ handlng cleanup
[openwrt/svn-archive/archive.git] / target / linux / ar7 / files / arch / mips / ar7 / irq.c
1 /*
2 * $Id$
3 *
4 * Copyright (C) 2006, 2007 OpenWrt.org
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23
24 #include <asm/irq_cpu.h>
25 #include <asm/mipsregs.h>
26 #include <asm/ar7/ar7.h>
27
28 #define EXCEPT_OFFSET 0x80
29 #define PACE_OFFSET 0xA0
30 #define CHNLS_OFFSET 0x200
31
32 #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
33 #define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
34 #define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
35 #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
36 #define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
37 #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
38 #define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
39 #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
40 #define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
41 #define PIR_OFFSET (0x40)
42 #define MSR_OFFSET (0x44)
43 #define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
44 #define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
45
46 #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
47
48 #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
49
50 static void ar7_unmask_irq(unsigned int irq_nr);
51 static void ar7_mask_irq(unsigned int irq_nr);
52 static void ar7_ack_irq(unsigned int irq_nr);
53 static void ar7_unmask_sec_irq(unsigned int irq_nr);
54 static void ar7_mask_sec_irq(unsigned int irq_nr);
55 static void ar7_ack_sec_irq(unsigned int irq_nr);
56 static void ar7_cascade(void);
57 static void ar7_irq_init(int base);
58 static int ar7_irq_base;
59
60 static struct irq_chip ar7_irq_type = {
61 .name = "AR7",
62 .unmask = ar7_unmask_irq,
63 .mask = ar7_mask_irq,
64 .ack = ar7_ack_irq
65 };
66
67 static struct irq_chip ar7_sec_irq_type = {
68 .name = "AR7",
69 .unmask = ar7_unmask_sec_irq,
70 .mask = ar7_mask_sec_irq,
71 .ack = ar7_ack_sec_irq,
72 };
73
74 static struct irqaction ar7_cascade_action = {
75 .handler = no_action,
76 .name = "AR7 cascade interrupt"
77 };
78
79 static struct irqaction ar7_sec_cascade_action = {
80 .handler = no_action,
81 .name = "AR7 secondary cascade interrupt"
82 };
83
84 static void ar7_unmask_irq(unsigned int irq)
85 {
86 writel(1 << ((irq - ar7_irq_base) % 32),
87 REG(ESR_OFFSET(irq - ar7_irq_base)));
88 }
89
90 static void ar7_mask_irq(unsigned int irq)
91 {
92 writel(1 << ((irq - ar7_irq_base) % 32),
93 REG(ECR_OFFSET(irq - ar7_irq_base)));
94 }
95
96 static void ar7_ack_irq(unsigned int irq)
97 {
98 writel(1 << ((irq - ar7_irq_base) % 32),
99 REG(CR_OFFSET(irq - ar7_irq_base)));
100 }
101
102 static void ar7_unmask_sec_irq(unsigned int irq)
103 {
104 writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
105 }
106
107 static void ar7_mask_sec_irq(unsigned int irq)
108 {
109 writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
110 }
111
112 static void ar7_ack_sec_irq(unsigned int irq)
113 {
114 writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
115 }
116
117 void __init arch_init_irq(void) {
118 mips_cpu_irq_init();
119 ar7_irq_init(8);
120 }
121
122 static void __init ar7_irq_init(int base)
123 {
124 int i;
125 /*
126 * Disable interrupts and clear pending
127 */
128 writel(0xffffffff, REG(ECR_OFFSET(0)));
129 writel(0xff, REG(ECR_OFFSET(32)));
130 writel(0xffffffff, REG(SEC_ECR_OFFSET));
131 writel(0xffffffff, REG(CR_OFFSET(0)));
132 writel(0xff, REG(CR_OFFSET(32)));
133 writel(0xffffffff, REG(SEC_CR_OFFSET));
134
135 ar7_irq_base = base;
136
137 for (i = 0; i < 40; i++) {
138 writel(i, REG(CHNL_OFFSET(i)));
139 /* Primary IRQ's */
140 set_irq_chip_and_handler(base + i, &ar7_irq_type,
141 handle_level_irq);
142 /* Secondary IRQ's */
143 if (i < 32)
144 set_irq_chip_and_handler(base + i + 40,
145 &ar7_sec_irq_type,
146 handle_level_irq);
147 }
148
149 setup_irq(2, &ar7_cascade_action);
150 setup_irq(ar7_irq_base, &ar7_sec_cascade_action);
151 set_c0_status(IE_IRQ0);
152 }
153
154 static void ar7_cascade(void)
155 {
156 u32 status;
157 int i, irq;
158
159 /* Primary IRQ's */
160 irq = readl(REG(PIR_OFFSET)) & 0x3f;
161 if (irq) {
162 do_IRQ(ar7_irq_base + irq);
163 return;
164 }
165
166 /* Secondary IRQ's are cascaded through primary '0' */
167 writel(1, REG(CR_OFFSET(irq)));
168 status = readl(REG(SEC_SR_OFFSET));
169 for (i = 0; i < 32; i++) {
170 if (status & 1) {
171 do_IRQ(ar7_irq_base + i + 40);
172 return;
173 }
174 status >>= 1;
175 }
176
177 spurious_interrupt();
178 }
179
180 asmlinkage void plat_irq_dispatch(void)
181 {
182 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
183 if (pending & STATUSF_IP7) /* cpu timer */
184 do_IRQ(7);
185 else if (pending & STATUSF_IP2) /* int0 hardware line */
186 ar7_cascade();
187 else
188 spurious_interrupt();
189 }