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small cpmac fixes
[openwrt/svn-archive/archive.git] / target / linux / ar7 / files / drivers / net / cpmac.c
1 /*
2 * Copyright (C) 2006, 2007 OpenWrt.org
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/moduleparam.h>
22
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/types.h>
28 #include <linux/delay.h>
29 #include <linux/version.h>
30
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/platform_device.h>
38 #include <linux/dma-mapping.h>
39 #include <asm/gpio.h>
40
41 MODULE_AUTHOR("Eugene Konev");
42 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
43 MODULE_LICENSE("GPL");
44
45 static int rx_ring_size = 64;
46 static int disable_napi;
47 static int debug_level = 8;
48 static int dumb_switch;
49
50 module_param(rx_ring_size, int, 0644);
51 module_param(disable_napi, int, 0644);
52 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
53 module_param(debug_level, int, 0444);
54 module_param(dumb_switch, int, 0444);
55
56 MODULE_PARM_DESC(rx_ring_size, "Size of rx ring (in skbs)");
57 MODULE_PARM_DESC(disable_napi, "Disable NAPI polling");
58 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
59 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
60
61 /* frame size + 802.1q tag */
62 #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4)
63 #define CPMAC_TX_RING_SIZE 8
64
65 /* Ethernet registers */
66 #define CPMAC_TX_CONTROL 0x0004
67 #define CPMAC_TX_TEARDOWN 0x0008
68 #define CPMAC_RX_CONTROL 0x0014
69 #define CPMAC_RX_TEARDOWN 0x0018
70 #define CPMAC_MBP 0x0100
71 # define MBP_RXPASSCRC 0x40000000
72 # define MBP_RXQOS 0x20000000
73 # define MBP_RXNOCHAIN 0x10000000
74 # define MBP_RXCMF 0x01000000
75 # define MBP_RXSHORT 0x00800000
76 # define MBP_RXCEF 0x00400000
77 # define MBP_RXPROMISC 0x00200000
78 # define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
79 # define MBP_RXBCAST 0x00002000
80 # define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
81 # define MBP_RXMCAST 0x00000020
82 # define MBP_MCASTCHAN(channel) ((channel) & 0x7)
83 #define CPMAC_UNICAST_ENABLE 0x0104
84 #define CPMAC_UNICAST_CLEAR 0x0108
85 #define CPMAC_MAX_LENGTH 0x010c
86 #define CPMAC_BUFFER_OFFSET 0x0110
87 #define CPMAC_MAC_CONTROL 0x0160
88 # define MAC_TXPTYPE 0x00000200
89 # define MAC_TXPACE 0x00000040
90 # define MAC_MII 0x00000020
91 # define MAC_TXFLOW 0x00000010
92 # define MAC_RXFLOW 0x00000008
93 # define MAC_MTEST 0x00000004
94 # define MAC_LOOPBACK 0x00000002
95 # define MAC_FDX 0x00000001
96 #define CPMAC_MAC_STATUS 0x0164
97 # define MAC_STATUS_QOS 0x00000004
98 # define MAC_STATUS_RXFLOW 0x00000002
99 # define MAC_STATUS_TXFLOW 0x00000001
100 #define CPMAC_TX_INT_ENABLE 0x0178
101 #define CPMAC_TX_INT_CLEAR 0x017c
102 #define CPMAC_MAC_INT_VECTOR 0x0180
103 # define MAC_INT_STATUS 0x00080000
104 # define MAC_INT_HOST 0x00040000
105 # define MAC_INT_RX 0x00020000
106 # define MAC_INT_TX 0x00010000
107 #define CPMAC_MAC_EOI_VECTOR 0x0184
108 #define CPMAC_RX_INT_ENABLE 0x0198
109 #define CPMAC_RX_INT_CLEAR 0x019c
110 #define CPMAC_MAC_INT_ENABLE 0x01a8
111 #define CPMAC_MAC_INT_CLEAR 0x01ac
112 #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
113 #define CPMAC_MAC_ADDR_MID 0x01d0
114 #define CPMAC_MAC_ADDR_HI 0x01d4
115 #define CPMAC_MAC_HASH_LO 0x01d8
116 #define CPMAC_MAC_HASH_HI 0x01dc
117 #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
118 #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
119 #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
120 #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
121 #define CPMAC_REG_END 0x0680
122 /*
123 * Rx/Tx statistics
124 * TODO: use some of them to fill stats in cpmac_stats()
125 */
126 #define CPMAC_STATS_RX_GOOD 0x0200
127 #define CPMAC_STATS_RX_BCAST 0x0204
128 #define CPMAC_STATS_RX_MCAST 0x0208
129 #define CPMAC_STATS_RX_PAUSE 0x020c
130 #define CPMAC_STATS_RX_CRC 0x0210
131 #define CPMAC_STATS_RX_ALIGN 0x0214
132 #define CPMAC_STATS_RX_OVER 0x0218
133 #define CPMAC_STATS_RX_JABBER 0x021c
134 #define CPMAC_STATS_RX_UNDER 0x0220
135 #define CPMAC_STATS_RX_FRAG 0x0224
136 #define CPMAC_STATS_RX_FILTER 0x0228
137 #define CPMAC_STATS_RX_QOSFILTER 0x022c
138 #define CPMAC_STATS_RX_OCTETS 0x0230
139
140 #define CPMAC_STATS_TX_GOOD 0x0234
141 #define CPMAC_STATS_TX_BCAST 0x0238
142 #define CPMAC_STATS_TX_MCAST 0x023c
143 #define CPMAC_STATS_TX_PAUSE 0x0240
144 #define CPMAC_STATS_TX_DEFER 0x0244
145 #define CPMAC_STATS_TX_COLLISION 0x0248
146 #define CPMAC_STATS_TX_SINGLECOLL 0x024c
147 #define CPMAC_STATS_TX_MULTICOLL 0x0250
148 #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
149 #define CPMAC_STATS_TX_LATECOLL 0x0258
150 #define CPMAC_STATS_TX_UNDERRUN 0x025c
151 #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
152 #define CPMAC_STATS_TX_OCTETS 0x0264
153
154 #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
155 #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
156 (reg)))
157
158 /* MDIO bus */
159 #define CPMAC_MDIO_VERSION 0x0000
160 #define CPMAC_MDIO_CONTROL 0x0004
161 # define MDIOC_IDLE 0x80000000
162 # define MDIOC_ENABLE 0x40000000
163 # define MDIOC_PREAMBLE 0x00100000
164 # define MDIOC_FAULT 0x00080000
165 # define MDIOC_FAULTDETECT 0x00040000
166 # define MDIOC_INTTEST 0x00020000
167 # define MDIOC_CLKDIV(div) ((div) & 0xff)
168 #define CPMAC_MDIO_ALIVE 0x0008
169 #define CPMAC_MDIO_LINK 0x000c
170 #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
171 # define MDIO_BUSY 0x80000000
172 # define MDIO_WRITE 0x40000000
173 # define MDIO_REG(reg) (((reg) & 0x1f) << 21)
174 # define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
175 # define MDIO_DATA(data) ((data) & 0xffff)
176 #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
177 # define PHYSEL_LINKSEL 0x00000040
178 # define PHYSEL_LINKINT 0x00000020
179
180 struct cpmac_desc {
181 u32 hw_next;
182 u32 hw_data;
183 u16 buflen;
184 u16 bufflags;
185 u16 datalen;
186 u16 dataflags;
187 #define CPMAC_SOP 0x8000
188 #define CPMAC_EOP 0x4000
189 #define CPMAC_OWN 0x2000
190 #define CPMAC_EOQ 0x1000
191 struct sk_buff *skb;
192 struct cpmac_desc *next;
193 dma_addr_t mapping;
194 dma_addr_t data_mapping;
195 };
196
197 struct cpmac_priv {
198 struct net_device_stats stats;
199 spinlock_t lock;
200 struct cpmac_desc *rx_head;
201 int tx_head, tx_tail;
202 struct cpmac_desc *desc_ring;
203 dma_addr_t dma_ring;
204 void __iomem *regs;
205 struct mii_bus *mii_bus;
206 struct phy_device *phy;
207 char phy_name[BUS_ID_SIZE];
208 struct plat_cpmac_data *config;
209 int oldlink, oldspeed, oldduplex;
210 u32 msg_enable;
211 struct net_device *dev;
212 struct work_struct alloc_work;
213 };
214
215 static irqreturn_t cpmac_irq(int, void *);
216 static void cpmac_reset(struct net_device *dev);
217 static void cpmac_hw_init(struct net_device *dev);
218 static int cpmac_stop(struct net_device *dev);
219 static int cpmac_open(struct net_device *dev);
220
221 static void cpmac_dump_regs(struct net_device *dev)
222 {
223 int i;
224 struct cpmac_priv *priv = netdev_priv(dev);
225 for (i = 0; i < CPMAC_REG_END; i += 4) {
226 if (i % 16 == 0) {
227 if (i)
228 printk("\n");
229 printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
230 priv->regs + i);
231 }
232 printk(" %08x", cpmac_read(priv->regs, i));
233 }
234 printk("\n");
235 }
236
237 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
238 {
239 int i;
240 printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
241 for (i = 0; i < sizeof(*desc) / 4; i++)
242 printk(" %08x", ((u32 *)desc)[i]);
243 printk("\n");
244 }
245
246 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
247 {
248 int i;
249 printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
250 for (i = 0; i < skb->len; i++) {
251 if (i % 16 == 0) {
252 if (i)
253 printk("\n");
254 printk(KERN_DEBUG "%s: data[%p]:", dev->name,
255 skb->data + i);
256 }
257 printk(" %02x", ((u8 *)skb->data)[i]);
258 }
259 printk("\n");
260 }
261
262 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
263 {
264 u32 val;
265
266 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
267 cpu_relax();
268 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
269 MDIO_PHY(phy_id));
270 while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
271 cpu_relax();
272 return MDIO_DATA(val);
273 }
274
275 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
276 int reg, u16 val)
277 {
278 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
279 cpu_relax();
280 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
281 MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
282 return 0;
283 }
284
285 static int cpmac_mdio_reset(struct mii_bus *bus)
286 {
287 ar7_device_reset(AR7_RESET_BIT_MDIO);
288 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
289 MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
290 return 0;
291 }
292
293 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
294
295 static struct mii_bus cpmac_mii = {
296 .name = "cpmac-mii",
297 .read = cpmac_mdio_read,
298 .write = cpmac_mdio_write,
299 .reset = cpmac_mdio_reset,
300 .irq = mii_irqs,
301 };
302
303 static int cpmac_config(struct net_device *dev, struct ifmap *map)
304 {
305 if (dev->flags & IFF_UP)
306 return -EBUSY;
307
308 /* Don't allow changing the I/O address */
309 if (map->base_addr != dev->base_addr)
310 return -EOPNOTSUPP;
311
312 /* ignore other fields */
313 return 0;
314 }
315
316 static int cpmac_set_mac_address(struct net_device *dev, void *addr)
317 {
318 struct sockaddr *sa = addr;
319
320 if (dev->flags & IFF_UP)
321 return -EBUSY;
322
323 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
324
325 return 0;
326 }
327
328 static void cpmac_set_multicast_list(struct net_device *dev)
329 {
330 struct dev_mc_list *iter;
331 int i;
332 u8 tmp;
333 u32 mbp, bit, hash[2] = { 0, };
334 struct cpmac_priv *priv = netdev_priv(dev);
335
336 mbp = cpmac_read(priv->regs, CPMAC_MBP);
337 if (dev->flags & IFF_PROMISC) {
338 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
339 MBP_RXPROMISC);
340 } else {
341 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
342 if (dev->flags & IFF_ALLMULTI) {
343 /* enable all multicast mode */
344 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
345 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
346 } else {
347 /*
348 * cpmac uses some strange mac address hashing
349 * (not crc32)
350 */
351 for (i = 0, iter = dev->mc_list; i < dev->mc_count;
352 i++, iter = iter->next) {
353 bit = 0;
354 tmp = iter->dmi_addr[0];
355 bit ^= (tmp >> 2) ^ (tmp << 4);
356 tmp = iter->dmi_addr[1];
357 bit ^= (tmp >> 4) ^ (tmp << 2);
358 tmp = iter->dmi_addr[2];
359 bit ^= (tmp >> 6) ^ tmp;
360 tmp = iter->dmi_addr[3];
361 bit ^= (tmp >> 2) ^ (tmp << 4);
362 tmp = iter->dmi_addr[4];
363 bit ^= (tmp >> 4) ^ (tmp << 2);
364 tmp = iter->dmi_addr[5];
365 bit ^= (tmp >> 6) ^ tmp;
366 bit &= 0x3f;
367 hash[bit / 32] |= 1 << (bit % 32);
368 }
369
370 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
371 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
372 }
373 }
374 }
375
376 static struct sk_buff *cpmac_rx_one(struct net_device *dev,
377 struct cpmac_priv *priv,
378 struct cpmac_desc *desc)
379 {
380 unsigned long flags;
381 struct sk_buff *skb, *result = NULL;
382
383 if (unlikely(netif_msg_hw(priv)))
384 cpmac_dump_desc(dev, desc);
385 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
386 if (unlikely(!desc->datalen)) {
387 if (netif_msg_rx_err(priv) && net_ratelimit())
388 printk(KERN_WARNING "%s: rx: spurious interrupt\n",
389 dev->name);
390 return NULL;
391 }
392
393 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
394 spin_lock_irqsave(&priv->lock, flags);
395 if (likely(skb)) {
396 skb_reserve(skb, 2);
397 skb_put(desc->skb, desc->datalen);
398 desc->skb->protocol = eth_type_trans(desc->skb, dev);
399 desc->skb->ip_summed = CHECKSUM_NONE;
400 priv->stats.rx_packets++;
401 priv->stats.rx_bytes += desc->datalen;
402 result = desc->skb;
403 dma_unmap_single(&dev->dev, desc->data_mapping, CPMAC_SKB_SIZE,
404 DMA_FROM_DEVICE);
405 desc->skb = skb;
406 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
407 CPMAC_SKB_SIZE,
408 DMA_FROM_DEVICE);
409 desc->hw_data = (u32)desc->data_mapping;
410 if (unlikely(netif_msg_pktdata(priv))) {
411 printk(KERN_DEBUG "%s: received packet:\n", dev->name);
412 cpmac_dump_skb(dev, result);
413 }
414 } else {
415 if (netif_msg_rx_err(priv) && net_ratelimit())
416 printk(KERN_WARNING
417 "%s: low on skbs, dropping packet\n", dev->name);
418 priv->stats.rx_dropped++;
419 }
420 spin_unlock_irqrestore(&priv->lock, flags);
421
422 desc->buflen = CPMAC_SKB_SIZE;
423 desc->dataflags = CPMAC_OWN;
424
425 return result;
426 }
427
428 static void cpmac_rx(struct net_device *dev)
429 {
430 struct sk_buff *skb;
431 struct cpmac_desc *desc;
432 struct cpmac_priv *priv = netdev_priv(dev);
433
434 spin_lock(&priv->lock);
435 if (unlikely(!priv->rx_head)) {
436 spin_unlock(&priv->lock);
437 return;
438 }
439
440 desc = priv->rx_head;
441
442 while ((desc->dataflags & CPMAC_OWN) == 0) {
443 skb = cpmac_rx_one(dev, priv, desc);
444 if (likely(skb))
445 netif_rx(skb);
446 desc = desc->next;
447 }
448
449 priv->rx_head = desc;
450 cpmac_write(priv->regs, CPMAC_RX_PTR(0), (u32)desc->mapping);
451 spin_unlock(&priv->lock);
452 }
453
454 static int cpmac_poll(struct net_device *dev, int *budget)
455 {
456 struct sk_buff *skb;
457 struct cpmac_desc *desc;
458 int received = 0, quota = min(dev->quota, *budget);
459 struct cpmac_priv *priv = netdev_priv(dev);
460
461 if (unlikely(!priv->rx_head)) {
462 if (netif_msg_rx_err(priv) && net_ratelimit())
463 printk(KERN_WARNING "%s: rx: polling, but no queue\n",
464 dev->name);
465 netif_rx_complete(dev);
466 return 0;
467 }
468
469 desc = priv->rx_head;
470
471 while ((received < quota) && ((desc->dataflags & CPMAC_OWN) == 0)) {
472 skb = cpmac_rx_one(dev, priv, desc);
473 if (likely(skb)) {
474 netif_receive_skb(skb);
475 received++;
476 }
477 desc = desc->next;
478 }
479
480 priv->rx_head = desc;
481 *budget -= received;
482 dev->quota -= received;
483 if (unlikely(netif_msg_rx_status(priv)))
484 printk(KERN_DEBUG "%s: poll processed %d packets\n", dev->name,
485 received);
486 if (desc->dataflags & CPMAC_OWN) {
487 netif_rx_complete(dev);
488 cpmac_write(priv->regs, CPMAC_RX_PTR(0), (u32)desc->mapping);
489 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
490 return 0;
491 }
492
493 return 1;
494 }
495
496 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
497 {
498 unsigned long flags;
499 int channel, len;
500 struct cpmac_desc *desc;
501 struct cpmac_priv *priv = netdev_priv(dev);
502
503 if (unlikely(skb_padto(skb, ETH_ZLEN))) {
504 if (netif_msg_tx_err(priv) && net_ratelimit())
505 printk(KERN_WARNING"%s: tx: padding failed, dropping\n",
506 dev->name);
507 spin_lock_irqsave(&priv->lock, flags);
508 priv->stats.tx_dropped++;
509 spin_unlock_irqrestore(&priv->lock, flags);
510 return -ENOMEM;
511 }
512
513 len = max(skb->len, ETH_ZLEN);
514 spin_lock_irqsave(&priv->lock, flags);
515 channel = priv->tx_tail++;
516 priv->tx_tail %= CPMAC_TX_RING_SIZE;
517 if (priv->tx_tail == priv->tx_head)
518 netif_stop_queue(dev);
519
520 desc = &priv->desc_ring[channel];
521 if (desc->dataflags & CPMAC_OWN) {
522 if (netif_msg_tx_err(priv) && net_ratelimit())
523 printk(KERN_WARNING "%s: tx dma ring full, dropping\n",
524 dev->name);
525 priv->stats.tx_dropped++;
526 spin_unlock_irqrestore(&priv->lock, flags);
527 dev_kfree_skb_any(skb);
528 return -ENOMEM;
529 }
530
531 dev->trans_start = jiffies;
532 spin_unlock_irqrestore(&priv->lock, flags);
533 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
534 desc->skb = skb;
535 desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
536 DMA_TO_DEVICE);
537 desc->hw_data = (u32)desc->data_mapping;
538 desc->datalen = len;
539 desc->buflen = len;
540 if (unlikely(netif_msg_tx_queued(priv)))
541 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
542 skb->len);
543 if (unlikely(netif_msg_hw(priv)))
544 cpmac_dump_desc(dev, desc);
545 if (unlikely(netif_msg_pktdata(priv)))
546 cpmac_dump_skb(dev, skb);
547 cpmac_write(priv->regs, CPMAC_TX_PTR(channel), (u32)desc->mapping);
548
549 return 0;
550 }
551
552 static void cpmac_end_xmit(struct net_device *dev, int channel)
553 {
554 struct cpmac_desc *desc;
555 struct cpmac_priv *priv = netdev_priv(dev);
556
557 spin_lock(&priv->lock);
558 desc = &priv->desc_ring[channel];
559 cpmac_write(priv->regs, CPMAC_TX_ACK(channel), (u32)desc->mapping);
560 if (likely(desc->skb)) {
561 priv->stats.tx_packets++;
562 priv->stats.tx_bytes += desc->skb->len;
563 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
564 DMA_TO_DEVICE);
565
566 if (unlikely(netif_msg_tx_done(priv)))
567 printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
568 desc->skb, desc->skb->len);
569
570 dev_kfree_skb_irq(desc->skb);
571 if (netif_queue_stopped(dev))
572 netif_wake_queue(dev);
573 } else
574 if (netif_msg_tx_err(priv) && net_ratelimit())
575 printk(KERN_WARNING
576 "%s: end_xmit: spurious interrupt\n", dev->name);
577 spin_unlock(&priv->lock);
578 }
579
580 static void cpmac_reset(struct net_device *dev)
581 {
582 int i;
583 struct cpmac_priv *priv = netdev_priv(dev);
584
585 ar7_device_reset(priv->config->reset_bit);
586 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
587 cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
588 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
589 cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
590 for (i = 0; i < 8; i++) {
591 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
592 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
593 }
594 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
595 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
596 }
597
598 static inline void cpmac_free_rx_ring(struct net_device *dev)
599 {
600 struct cpmac_desc *desc;
601 int i;
602 struct cpmac_priv *priv = netdev_priv(dev);
603
604 if (unlikely(!priv->rx_head))
605 return;
606
607 desc = priv->rx_head;
608
609 for (i = 0; i < rx_ring_size; i++) {
610 desc->buflen = CPMAC_SKB_SIZE;
611 if ((desc->dataflags & CPMAC_OWN) == 0) {
612 if (netif_msg_rx_err(priv) && net_ratelimit())
613 printk(KERN_WARNING "%s: packet dropped\n",
614 dev->name);
615 if (unlikely(netif_msg_hw(priv)))
616 cpmac_dump_desc(dev, desc);
617 desc->dataflags = CPMAC_OWN;
618 priv->stats.rx_dropped++;
619 }
620 desc = desc->next;
621 }
622 }
623
624 static irqreturn_t cpmac_irq(int irq, void *dev_id)
625 {
626 struct net_device *dev = dev_id;
627 struct cpmac_priv *priv;
628 u32 status;
629
630 if (!dev)
631 return IRQ_NONE;
632
633 priv = netdev_priv(dev);
634
635 status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
636
637 if (unlikely(netif_msg_intr(priv)))
638 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
639 status);
640
641 if (status & MAC_INT_TX)
642 cpmac_end_xmit(dev, (status & 7));
643
644 if (status & MAC_INT_RX) {
645 if (disable_napi)
646 cpmac_rx(dev);
647 else {
648 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1);
649 netif_rx_schedule(dev);
650 }
651 }
652
653 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
654
655 if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS))) {
656 if (netif_msg_drv(priv) && net_ratelimit())
657 printk(KERN_ERR "%s: hw error, resetting...\n",
658 dev->name);
659 if (unlikely(netif_msg_hw(priv)))
660 cpmac_dump_regs(dev);
661 spin_lock(&priv->lock);
662 phy_stop(priv->phy);
663 cpmac_reset(dev);
664 cpmac_free_rx_ring(dev);
665 cpmac_hw_init(dev);
666 spin_unlock(&priv->lock);
667 }
668
669 return IRQ_HANDLED;
670 }
671
672 static void cpmac_tx_timeout(struct net_device *dev)
673 {
674 struct cpmac_priv *priv = netdev_priv(dev);
675 struct cpmac_desc *desc;
676
677 priv->stats.tx_errors++;
678 desc = &priv->desc_ring[priv->tx_head++];
679 priv->tx_head %= 8;
680 if (netif_msg_tx_err(priv) && net_ratelimit())
681 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
682 if (desc->skb)
683 dev_kfree_skb_any(desc->skb);
684 netif_wake_queue(dev);
685 }
686
687 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
688 {
689 struct cpmac_priv *priv = netdev_priv(dev);
690 if (!(netif_running(dev)))
691 return -EINVAL;
692 if (!priv->phy)
693 return -EINVAL;
694 if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
695 (cmd == SIOCSMIIREG))
696 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
697
698 return -EINVAL;
699 }
700
701 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
702 {
703 struct cpmac_priv *priv = netdev_priv(dev);
704
705 if (priv->phy)
706 return phy_ethtool_gset(priv->phy, cmd);
707
708 return -EINVAL;
709 }
710
711 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
712 {
713 struct cpmac_priv *priv = netdev_priv(dev);
714
715 if (!capable(CAP_NET_ADMIN))
716 return -EPERM;
717
718 if (priv->phy)
719 return phy_ethtool_sset(priv->phy, cmd);
720
721 return -EINVAL;
722 }
723
724 static void cpmac_get_drvinfo(struct net_device *dev,
725 struct ethtool_drvinfo *info)
726 {
727 strcpy(info->driver, "cpmac");
728 strcpy(info->version, "0.0.3");
729 info->fw_version[0] = '\0';
730 sprintf(info->bus_info, "%s", "cpmac");
731 info->regdump_len = 0;
732 }
733
734 static const struct ethtool_ops cpmac_ethtool_ops = {
735 .get_settings = cpmac_get_settings,
736 .set_settings = cpmac_set_settings,
737 .get_drvinfo = cpmac_get_drvinfo,
738 .get_link = ethtool_op_get_link,
739 };
740
741 static struct net_device_stats *cpmac_stats(struct net_device *dev)
742 {
743 struct cpmac_priv *priv = netdev_priv(dev);
744
745 if (netif_device_present(dev))
746 return &priv->stats;
747
748 return NULL;
749 }
750
751 static int cpmac_change_mtu(struct net_device *dev, int mtu)
752 {
753 unsigned long flags;
754 struct cpmac_priv *priv = netdev_priv(dev);
755 spinlock_t *lock = &priv->lock;
756
757 if ((mtu < 68) || (mtu > 1500))
758 return -EINVAL;
759
760 spin_lock_irqsave(lock, flags);
761 dev->mtu = mtu;
762 spin_unlock_irqrestore(lock, flags);
763
764 return 0;
765 }
766
767 static void cpmac_adjust_link(struct net_device *dev)
768 {
769 struct cpmac_priv *priv = netdev_priv(dev);
770 unsigned long flags;
771 int new_state = 0;
772
773 spin_lock_irqsave(&priv->lock, flags);
774 if (priv->phy->link) {
775 if (priv->phy->duplex != priv->oldduplex) {
776 new_state = 1;
777 priv->oldduplex = priv->phy->duplex;
778 }
779
780 if (priv->phy->speed != priv->oldspeed) {
781 new_state = 1;
782 priv->oldspeed = priv->phy->speed;
783 }
784
785 if (!priv->oldlink) {
786 new_state = 1;
787 priv->oldlink = 1;
788 netif_schedule(dev);
789 }
790 } else if (priv->oldlink) {
791 new_state = 1;
792 priv->oldlink = 0;
793 priv->oldspeed = 0;
794 priv->oldduplex = -1;
795 }
796
797 if (new_state && netif_msg_link(priv) && net_ratelimit())
798 phy_print_status(priv->phy);
799
800 spin_unlock_irqrestore(&priv->lock, flags);
801 }
802
803 static void cpmac_hw_init(struct net_device *dev)
804 {
805 int i;
806 struct cpmac_priv *priv = netdev_priv(dev);
807
808 for (i = 0; i < 8; i++) {
809 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
810 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
811 }
812 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
813
814 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
815 MBP_RXMCAST);
816 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
817 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xfe);
818 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
819 for (i = 0; i < 8; i++)
820 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
821 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
822 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
823 (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
824 (dev->dev_addr[3] << 24));
825 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
826 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
827 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
828 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
829 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
830 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
831 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
832
833 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
834 cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
835 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
836 cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
837 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
838 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
839 MAC_FDX);
840
841 priv->phy->state = PHY_CHANGELINK;
842 phy_start(priv->phy);
843 }
844
845 static int cpmac_open(struct net_device *dev)
846 {
847 int i, size, res;
848 struct cpmac_priv *priv = netdev_priv(dev);
849 struct cpmac_desc *desc;
850 struct sk_buff *skb;
851
852 priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link,
853 0, PHY_INTERFACE_MODE_MII);
854 if (IS_ERR(priv->phy)) {
855 if (netif_msg_drv(priv))
856 printk(KERN_ERR "%s: Could not attach to PHY\n",
857 dev->name);
858 return PTR_ERR(priv->phy);
859 }
860
861 if (!request_mem_region(dev->mem_start, dev->mem_end -
862 dev->mem_start, dev->name)) {
863 if (netif_msg_drv(priv))
864 printk(KERN_ERR "%s: failed to request registers\n",
865 dev->name);
866 res = -ENXIO;
867 goto fail_reserve;
868 }
869
870 priv->regs = ioremap(dev->mem_start, dev->mem_end -
871 dev->mem_start);
872 if (!priv->regs) {
873 if (netif_msg_drv(priv))
874 printk(KERN_ERR "%s: failed to remap registers\n",
875 dev->name);
876 res = -ENXIO;
877 goto fail_remap;
878 }
879
880 priv->rx_head = NULL;
881 size = rx_ring_size + CPMAC_TX_RING_SIZE;
882 priv->desc_ring = dma_alloc_coherent(&dev->dev,
883 sizeof(struct cpmac_desc) * size,
884 &priv->dma_ring,
885 GFP_KERNEL);
886 if (!priv->desc_ring) {
887 res = -ENOMEM;
888 goto fail_alloc;
889 }
890
891 priv->rx_head = &priv->desc_ring[CPMAC_TX_RING_SIZE];
892 for (i = 0; i < size; i++)
893 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
894
895 for (i = 0, desc = &priv->rx_head[i]; i < rx_ring_size; i++, desc++) {
896 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
897 if (unlikely(!skb)) {
898 res = -ENOMEM;
899 goto fail_desc;
900 }
901 skb_reserve(skb, 2);
902 desc->skb = skb;
903 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
904 CPMAC_SKB_SIZE,
905 DMA_FROM_DEVICE);
906 desc->hw_data = (u32)desc->data_mapping;
907 desc->buflen = CPMAC_SKB_SIZE;
908 desc->dataflags = CPMAC_OWN;
909 desc->next = &priv->rx_head[(i + 1) % rx_ring_size];
910 desc->hw_next = (u32)desc->next->mapping;
911 }
912
913 if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
914 dev->name, dev))) {
915 if (netif_msg_drv(priv))
916 printk(KERN_ERR "%s: failed to obtain irq\n",
917 dev->name);
918 goto fail_irq;
919 }
920
921 cpmac_reset(dev);
922 cpmac_hw_init(dev);
923
924 netif_start_queue(dev);
925 return 0;
926
927 fail_irq:
928 fail_desc:
929 for (i = 0; i < rx_ring_size; i++) {
930 if (priv->rx_head[i].skb) {
931 kfree_skb(priv->rx_head[i].skb);
932 dma_unmap_single(&dev->dev,
933 priv->rx_head[i].data_mapping,
934 CPMAC_SKB_SIZE,
935 DMA_FROM_DEVICE);
936 }
937 }
938 fail_alloc:
939 kfree(priv->desc_ring);
940 iounmap(priv->regs);
941
942 fail_remap:
943 release_mem_region(dev->mem_start, dev->mem_end -
944 dev->mem_start);
945
946 fail_reserve:
947 phy_disconnect(priv->phy);
948
949 return res;
950 }
951
952 static int cpmac_stop(struct net_device *dev)
953 {
954 int i;
955 struct cpmac_priv *priv = netdev_priv(dev);
956
957 netif_stop_queue(dev);
958
959 phy_stop(priv->phy);
960 phy_disconnect(priv->phy);
961 priv->phy = NULL;
962
963 cpmac_reset(dev);
964
965 for (i = 0; i < 8; i++)
966 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
967 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
968 cpmac_write(priv->regs, CPMAC_MBP, 0);
969
970 free_irq(dev->irq, dev);
971 release_mem_region(dev->mem_start, dev->mem_end -
972 dev->mem_start);
973 priv->rx_head = &priv->desc_ring[CPMAC_TX_RING_SIZE];
974 for (i = 0; i < rx_ring_size; i++) {
975 if (priv->rx_head[i].skb) {
976 kfree_skb(priv->rx_head[i].skb);
977 dma_unmap_single(&dev->dev,
978 priv->rx_head[i].data_mapping,
979 CPMAC_SKB_SIZE,
980 DMA_FROM_DEVICE);
981 }
982 }
983
984 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
985 (CPMAC_TX_RING_SIZE + rx_ring_size),
986 priv->desc_ring, priv->dma_ring);
987 return 0;
988 }
989
990 static int external_switch;
991
992 static int __devinit cpmac_probe(struct platform_device *pdev)
993 {
994 int i, rc, phy_id;
995 struct resource *res;
996 struct cpmac_priv *priv;
997 struct net_device *dev;
998 struct plat_cpmac_data *pdata;
999
1000 pdata = pdev->dev.platform_data;
1001
1002 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1003 if (!(pdata->phy_mask & (1 << phy_id)))
1004 continue;
1005 if (!cpmac_mii.phy_map[phy_id])
1006 continue;
1007 break;
1008 }
1009
1010 if (phy_id == PHY_MAX_ADDR) {
1011 if (external_switch || dumb_switch)
1012 phy_id = 0;
1013 else {
1014 printk(KERN_ERR "cpmac: no PHY present\n");
1015 return -ENODEV;
1016 }
1017 }
1018
1019 dev = alloc_etherdev(sizeof(struct cpmac_priv));
1020
1021 if (!dev) {
1022 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1023 return -ENOMEM;
1024 }
1025
1026 platform_set_drvdata(pdev, dev);
1027 priv = netdev_priv(dev);
1028
1029 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1030 if (!res) {
1031 rc = -ENODEV;
1032 goto fail;
1033 }
1034
1035 dev->mem_start = res->start;
1036 dev->mem_end = res->end;
1037 dev->irq = platform_get_irq_byname(pdev, "irq");
1038
1039 dev->open = cpmac_open;
1040 dev->stop = cpmac_stop;
1041 dev->set_config = cpmac_config;
1042 dev->hard_start_xmit = cpmac_start_xmit;
1043 dev->do_ioctl = cpmac_ioctl;
1044 dev->get_stats = cpmac_stats;
1045 dev->change_mtu = cpmac_change_mtu;
1046 dev->set_mac_address = cpmac_set_mac_address;
1047 dev->set_multicast_list = cpmac_set_multicast_list;
1048 dev->tx_timeout = cpmac_tx_timeout;
1049 dev->ethtool_ops = &cpmac_ethtool_ops;
1050 if (!disable_napi) {
1051 dev->poll = cpmac_poll;
1052 dev->weight = min(rx_ring_size, 64);
1053 }
1054
1055 spin_lock_init(&priv->lock);
1056 priv->msg_enable = netif_msg_init(debug_level, 0xff);
1057 priv->config = pdata;
1058 priv->dev = dev;
1059 memcpy(dev->dev_addr, priv->config->dev_addr, sizeof(dev->dev_addr));
1060 if (phy_id == 31) {
1061 snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT,
1062 cpmac_mii.id, phy_id);
1063 /* cpmac_write(cpmac_mii.priv, CPMAC_MDIO_PHYSEL(0), PHYSEL_LINKSEL
1064 | PHYSEL_LINKINT | phy_id);*/
1065 } else
1066 snprintf(priv->phy_name, BUS_ID_SIZE, "fixed@%d:%d", 100, 1);
1067
1068 if ((rc = register_netdev(dev))) {
1069 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1070 dev->name);
1071 goto fail;
1072 }
1073
1074 if (netif_msg_probe(priv)) {
1075 printk(KERN_INFO
1076 "cpmac: device %s (regs: %p, irq: %d, phy: %s, mac: ",
1077 dev->name, (u32 *)dev->mem_start, dev->irq,
1078 priv->phy_name);
1079 for (i = 0; i < 6; i++)
1080 printk("%02x%s", dev->dev_addr[i], i < 5 ? ":" : ")\n");
1081 }
1082 return 0;
1083
1084 fail:
1085 free_netdev(dev);
1086 return rc;
1087 }
1088
1089 static int __devexit cpmac_remove(struct platform_device *pdev)
1090 {
1091 struct net_device *dev = platform_get_drvdata(pdev);
1092 unregister_netdev(dev);
1093 free_netdev(dev);
1094 return 0;
1095 }
1096
1097 static struct platform_driver cpmac_driver = {
1098 .driver.name = "cpmac",
1099 .probe = cpmac_probe,
1100 .remove = __devexit_p(cpmac_remove),
1101 };
1102
1103 int __devinit cpmac_init(void)
1104 {
1105 u32 mask;
1106 int i, res;
1107
1108 cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1109
1110 if (!cpmac_mii.priv) {
1111 printk(KERN_ERR "Can't ioremap mdio registers\n");
1112 return -ENXIO;
1113 }
1114
1115 #warning FIXME: unhardcode gpio&reset bits
1116 ar7_gpio_disable(26);
1117 ar7_gpio_disable(27);
1118 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1119 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1120 ar7_device_reset(AR7_RESET_BIT_EPHY);
1121
1122 cpmac_mii.reset(&cpmac_mii);
1123
1124 for (i = 0; i < 300000; i++)
1125 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1126 break;
1127 else
1128 cpu_relax();
1129
1130 mask &= 0x7fffffff;
1131 if (mask & (mask - 1)) {
1132 external_switch = 1;
1133 mask = 0;
1134 }
1135
1136 cpmac_mii.phy_mask = ~(mask | 0x80000000);
1137
1138 res = mdiobus_register(&cpmac_mii);
1139 if (res)
1140 goto fail_mii;
1141
1142 res = platform_driver_register(&cpmac_driver);
1143 if (res)
1144 goto fail_cpmac;
1145
1146 return 0;
1147
1148 fail_cpmac:
1149 mdiobus_unregister(&cpmac_mii);
1150
1151 fail_mii:
1152 iounmap(cpmac_mii.priv);
1153
1154 return res;
1155 }
1156
1157 void __devexit cpmac_exit(void)
1158 {
1159 platform_driver_unregister(&cpmac_driver);
1160 mdiobus_unregister(&cpmac_mii);
1161 iounmap(cpmac_mii.priv);
1162 }
1163
1164 module_init(cpmac_init);
1165 module_exit(cpmac_exit);
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