target/linux/ar7/files/include/asm-mips/ar7/ar7.h

   1 /*
   2  * Copyright (C) 2006, 2007 OpenWrt.org
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #ifndef __AR7_H__
  20 #define __AR7_H__
  21
  22 #include <linux/delay.h>
  23 #include <asm/addrspace.h>
  24 #include <linux/io.h>
  25
  26 #define AR7_REGS_BASE   0x08610000
  27
  28 #define AR7_REGS_MAC0   (AR7_REGS_BASE + 0x0000)
  29 #define AR7_REGS_GPIO   (AR7_REGS_BASE + 0x0900)
  30 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
  31 #define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00)
  32 #define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
  33 #define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
  34 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
  35 #define AR7_REGS_DCL    (AR7_REGS_BASE + 0x1a00)
  36 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
  37 #define AR7_REGS_MDIO   (AR7_REGS_BASE + 0x1e00)
  38 #define AR7_REGS_IRQ    (AR7_REGS_BASE + 0x2400)
  39 #define AR7_REGS_MAC1   (AR7_REGS_BASE + 0x2800)
  40
  41 #define AR7_REGS_WDT    (AR7_REGS_BASE + 0x1f00)
  42 #define UR8_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
  43 #define UR8_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
  44
  45 #define AR7_RESET_PEREPHERIAL   0x0
  46 #define AR7_RESET_SOFTWARE      0x4
  47 #define AR7_RESET_STATUS        0x8
  48
  49 #define AR7_RESET_BIT_CPMAC_LO  17
  50 #define AR7_RESET_BIT_CPMAC_HI  21
  51 #define AR7_RESET_BIT_MDIO      22
  52 #define AR7_RESET_BIT_EPHY      26
  53
  54 /* GPIO control registers */
  55 #define AR7_GPIO_INPUT  0x0
  56 #define AR7_GPIO_OUTPUT 0x4
  57 #define AR7_GPIO_DIR    0x8
  58 #define AR7_GPIO_ENABLE 0xc
  59
  60 #define AR7_CHIP_7100   0x18
  61 #define AR7_CHIP_7200   0x2b
  62 #define AR7_CHIP_7300   0x05
  63
  64 /* Interrupts */
  65 #define AR7_IRQ_UART0   15
  66 #define AR7_IRQ_UART1   16
  67
  68 /* Clocks */
  69 #define AR7_AFE_CLOCK   35328000
  70 #define AR7_REF_CLOCK   25000000
  71 #define AR7_XTAL_CLOCK  24000000
  72
  73 struct plat_cpmac_data {
  74         int reset_bit;
  75         int power_bit;
  76         u32 phy_mask;
  77         char dev_addr[6];
  78 };
  79
  80 struct plat_dsl_data {
  81         int reset_bit_dsl;
  82         int reset_bit_sar;
  83 };
  84
  85 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
  86
  87 static inline u16 ar7_chip_id(void)
  88 {
  89         return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
  90 }
  91
  92 static inline u8 ar7_chip_rev(void)
  93 {
  94         return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
  95 }
  96
  97 static inline int ar7_cpu_freq(void)
  98 {
  99         return ar7_cpu_clock;
 100 }
 101
 102 static inline int ar7_bus_freq(void)
 103 {
 104         return ar7_bus_clock;
 105 }
 106
 107 static inline int ar7_vbus_freq(void)
 108 {
 109         return ar7_bus_clock / 2;
 110 }
 111 #define ar7_cpmac_freq ar7_vbus_freq
 112
 113 static inline int ar7_dsp_freq(void)
 114 {
 115         return ar7_dsp_clock;
 116 }
 117
 118 static inline int ar7_has_high_cpmac(void)
 119 {
 120         u16 chip_id = ar7_chip_id();
 121         switch (chip_id) {
 122         case AR7_CHIP_7100:
 123         case AR7_CHIP_7200:
 124                 return 0;
 125         default:
 126                 return 1;
 127         }
 128 }
 129 #define ar7_has_high_vlynq ar7_has_high_cpmac
 130 #define ar7_has_second_uart ar7_has_high_cpmac
 131
 132 static inline void ar7_device_enable(u32 bit)
 133 {
 134         void *reset_reg =
 135                 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
 136         writel(readl(reset_reg) | (1 << bit), reset_reg);
 137         mdelay(20);
 138 }
 139
 140 static inline void ar7_device_disable(u32 bit)
 141 {
 142         void *reset_reg =
 143                 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
 144         writel(readl(reset_reg) & ~(1 << bit), reset_reg);
 145         mdelay(20);
 146 }
 147
 148 static inline void ar7_device_reset(u32 bit)
 149 {
 150         ar7_device_disable(bit);
 151         ar7_device_enable(bit);
 152 }
 153
 154 static inline void ar7_device_on(u32 bit)
 155 {
 156         void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
 157         writel(readl(power_reg) | (1 << bit), power_reg);
 158         mdelay(20);
 159 }
 160
 161 static inline void ar7_device_off(u32 bit)
 162 {
 163         void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
 164         writel(readl(power_reg) & ~(1 << bit), power_reg);
 165         mdelay(20);
 166 }
 167
 168 #endif /* __AR7_H__ */