target/linux/ar7/patches-2.6.25/100-board_support.patch

   1 Index: linux-2.6.25.1/arch/mips/Kconfig
   2 ===================================================================
   3 --- linux-2.6.25.1.orig/arch/mips/Kconfig       2008-05-01 23:45:25.000000000 +0200
   4 +++ linux-2.6.25.1/arch/mips/Kconfig    2008-05-03 16:17:54.000000000 +0200
   5 @@ -18,6 +18,24 @@
   6         prompt "System type"
   7         default SGI_IP22
   8
   9 +config AR7
  10 +       bool "Texas Instruments AR7"
  11 +       select BOOT_ELF32
  12 +       select DMA_NONCOHERENT
  13 +       select CEVT_R4K
  14 +       select CSRC_R4K
  15 +       select IRQ_CPU
  16 +       select NO_EXCEPT_FILL
  17 +       select SWAP_IO_SPACE
  18 +       select SYS_HAS_CPU_MIPS32_R1
  19 +       select SYS_HAS_EARLY_PRINTK
  20 +       select SYS_SUPPORTS_32BIT_KERNEL
  21 +       select SYS_SUPPORTS_KGDB
  22 +       select SYS_SUPPORTS_LITTLE_ENDIAN
  23 +       select SYS_SUPPORTS_BIG_ENDIAN
  24 +       select GENERIC_GPIO
  25 +       select GENERIC_HARDIRQS_NO__DO_IRQ
  26 +
  27  config MACH_ALCHEMY
  28         bool "Alchemy processor based machines"
  29
  30 Index: linux-2.6.25.1/arch/mips/kernel/traps.c
  31 ===================================================================
  32 --- linux-2.6.25.1.orig/arch/mips/kernel/traps.c        2008-05-01 23:45:25.000000000 +0200
  33 +++ linux-2.6.25.1/arch/mips/kernel/traps.c     2008-05-03 16:17:54.000000000 +0200
  34 @@ -1112,9 +1112,22 @@
  35
  36         exception_handlers[n] = handler;
  37         if (n == 0 && cpu_has_divec) {
  38 -               *(u32 *)(ebase + 0x200) = 0x08000000 |
  39 -                                         (0x03ffffff & (handler >> 2));
  40 -               flush_icache_range(ebase + 0x200, ebase + 0x204);
  41 +               if ((handler ^ (ebase + 4)) & 0xfc000000) {
  42 +                       /* lui k0, 0x0000 */
  43 +                       *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16);
  44 +                       /* ori k0, 0x0000 */
  45 +                       *(u32 *)(ebase + 0x204) =
  46 +                                       0x375a0000 | (handler & 0xffff);
  47 +                       /* jr k0 */
  48 +                       *(u32 *)(ebase + 0x208) = 0x03400008;
  49 +                       /* nop */
  50 +                       *(u32 *)(ebase + 0x20C) = 0x00000000;
  51 +                       flush_icache_range(ebase + 0x200, ebase + 0x210);
  52 +               } else {
  53 +                       *(u32 *)(ebase + 0x200) =
  54 +                               0x08000000 | (0x03ffffff & (handler >> 2));
  55 +                       flush_icache_range(ebase + 0x200, ebase + 0x204);
  56 +               }
  57         }
  58         return (void *)old_handler;
  59  }
  60 Index: linux-2.6.25.1/arch/mips/Makefile
  61 ===================================================================
  62 --- linux-2.6.25.1.orig/arch/mips/Makefile      2008-05-01 23:45:25.000000000 +0200
  63 +++ linux-2.6.25.1/arch/mips/Makefile   2008-05-03 16:17:54.000000000 +0200
  64 @@ -167,6 +167,13 @@
  65  #
  66
  67  #
  68 +# Texas Instruments AR7
  69 +#
  70 +core-$(CONFIG_AR7)             += arch/mips/ar7/
  71 +cflags-$(CONFIG_AR7)           += -Iinclude/asm-mips/ar7
  72 +load-$(CONFIG_AR7)             += 0xffffffff94100000
  73 +
  74 +#
  75  # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
  76  #
  77  core-$(CONFIG_MACH_JAZZ)       += arch/mips/jazz/
  78 Index: linux-2.6.25.1/include/asm-mips/page.h
  79 ===================================================================
  80 --- linux-2.6.25.1.orig/include/asm-mips/page.h 2008-05-01 23:45:25.000000000 +0200
  81 +++ linux-2.6.25.1/include/asm-mips/page.h      2008-05-03 16:17:54.000000000 +0200
  82 @@ -182,8 +182,10 @@
  83  #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \
  84                                  VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
  85
  86 -#define UNCAC_ADDR(addr)       ((addr) - PAGE_OFFSET + UNCAC_BASE)
  87 -#define CAC_ADDR(addr)         ((addr) - UNCAC_BASE + PAGE_OFFSET)
  88 +#define UNCAC_ADDR(addr)       ((addr) - PAGE_OFFSET + UNCAC_BASE +    \
  89 +                                PHYS_OFFSET)
  90 +#define CAC_ADDR(addr)         ((addr) - UNCAC_BASE + PAGE_OFFSET -    \
  91 +                                PHYS_OFFSET)
  92
  93  #include <asm-generic/memory_model.h>
  94  #include <asm-generic/page.h>