target/linux/ar7/patches-2.6.32/930-titan-platform.patch

   1 Index: linux-2.6.32.7/arch/mips/ar7/platform.c
   2 ===================================================================
   3 --- linux-2.6.32.7.orig/arch/mips/ar7/platform.c        2010-01-29 00:06:20.000000000 +0100
   4 +++ linux-2.6.32.7/arch/mips/ar7/platform.c     2010-02-04 14:40:23.000000000 +0100
   5 @@ -131,6 +131,36 @@
   6         },
   7  };
   8
   9 +static struct resource cpmac_low_res_titan[] = {
  10 +       {
  11 +               .name = "regs",
  12 +               .flags = IORESOURCE_MEM,
  13 +               .start = TITAN_REGS_MAC0,
  14 +               .end = TITAN_REGS_MAC0 + 0x7ff,
  15 +       },
  16 +       {
  17 +               .name = "irq",
  18 +               .flags = IORESOURCE_IRQ,
  19 +               .start = 27,
  20 +               .end = 27,
  21 +       },
  22 +};
  23 +
  24 +static struct resource cpmac_high_res_titan[] = {
  25 +       {
  26 +               .name = "regs",
  27 +               .flags = IORESOURCE_MEM,
  28 +               .start = TITAN_REGS_MAC1,
  29 +               .end = TITAN_REGS_MAC1 + 0x7ff,
  30 +       },
  31 +       {
  32 +               .name = "irq",
  33 +               .flags = IORESOURCE_IRQ,
  34 +               .start = 41,
  35 +               .end = 41,
  36 +       },
  37 +};
  38 +
  39  static struct resource vlynq_low_res[] = {
  40         {
  41                 .name = "regs",
  42 @@ -185,6 +215,60 @@
  43         },
  44  };
  45
  46 +static struct resource vlynq_low_res_titan[] = {
  47 +       {
  48 +               .name = "regs",
  49 +               .flags = IORESOURCE_MEM,
  50 +               .start = TITAN_REGS_VLYNQ0,
  51 +               .end = TITAN_REGS_VLYNQ0 + 0xff,
  52 +       },
  53 +       {
  54 +               .name = "irq",
  55 +               .flags = IORESOURCE_IRQ,
  56 +               .start = 33,
  57 +               .end = 33,
  58 +       },
  59 +       {
  60 +               .name = "mem",
  61 +               .flags = IORESOURCE_MEM,
  62 +               .start = 0x0c000000,
  63 +               .end = 0x0fffffff,
  64 +       },
  65 +       {
  66 +               .name = "devirq",
  67 +               .flags = IORESOURCE_IRQ,
  68 +               .start = 80,
  69 +               .end = 111,
  70 +       },
  71 +};
  72 +
  73 +static struct resource vlynq_high_res_titan[] = {
  74 +       {
  75 +               .name = "regs",
  76 +               .flags = IORESOURCE_MEM,
  77 +               .start = TITAN_REGS_VLYNQ1,
  78 +               .end = TITAN_REGS_VLYNQ1 + 0xff,
  79 +       },
  80 +       {
  81 +               .name = "irq",
  82 +               .flags = IORESOURCE_IRQ,
  83 +               .start = 34,
  84 +               .end = 34,
  85 +       },
  86 +       {
  87 +               .name = "mem",
  88 +               .flags = IORESOURCE_MEM,
  89 +               .start = 0x40000000,
  90 +               .end = 0x43ffffff,
  91 +       },
  92 +       {
  93 +               .name = "devirq",
  94 +               .flags = IORESOURCE_IRQ,
  95 +               .start = 112,
  96 +               .end = 143,
  97 +       },
  98 +};
  99 +
 100  static struct resource usb_res[] = {
 101         {
 102                 .name = "regs",
 103 @@ -228,6 +312,18 @@
 104         .phy_mask = 0x7fffffff,
 105  };
 106
 107 +static struct plat_cpmac_data cpmac_low_data_titan = {
 108 +       .reset_bit = 17,
 109 +       .power_bit = 20,
 110 +       .phy_mask = 0x40000000,
 111 +};
 112 +
 113 +static struct plat_cpmac_data cpmac_high_data_titan = {
 114 +       .reset_bit = 21,
 115 +       .power_bit = 22,
 116 +       .phy_mask = 0x80000000,
 117 +};
 118 +
 119  static struct plat_vlynq_data vlynq_low_data = {
 120         .ops.on = vlynq_on,
 121         .ops.off = vlynq_off,
 122 @@ -242,6 +338,20 @@
 123         .gpio_bit = 19,
 124  };
 125
 126 +static struct plat_vlynq_data vlynq_low_data_titan = {
 127 +       .ops.on = vlynq_on,
 128 +       .ops.off = vlynq_off,
 129 +       .reset_bit = 15,
 130 +       .gpio_bit = 14,
 131 +};
 132 +
 133 +static struct plat_vlynq_data vlynq_high_data_titan = {
 134 +       .ops.on = vlynq_on,
 135 +       .ops.off = vlynq_off,
 136 +       .reset_bit = 16,
 137 +       .gpio_bit = 7,
 138 +};
 139 +
 140  static struct platform_device physmap_flash = {
 141         .id = 0,
 142         .name = "physmap-flash",
 143 @@ -275,6 +385,30 @@
 144         .num_resources = ARRAY_SIZE(cpmac_high_res),
 145  };
 146
 147 +static struct platform_device cpmac_low_titan = {
 148 +       .id = 0,
 149 +       .name = "cpmac",
 150 +       .dev = {
 151 +               .dma_mask = &cpmac_dma_mask,
 152 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 153 +               .platform_data = &cpmac_low_data_titan,
 154 +       },
 155 +       .resource = cpmac_low_res_titan,
 156 +       .num_resources = ARRAY_SIZE(cpmac_low_res_titan),
 157 +};
 158 +
 159 +static struct platform_device cpmac_high_titan = {
 160 +       .id = 1,
 161 +       .name = "cpmac",
 162 +       .dev = {
 163 +               .dma_mask = &cpmac_dma_mask,
 164 +               .coherent_dma_mask = DMA_BIT_MASK(32),
 165 +               .platform_data = &cpmac_high_data_titan,
 166 +       },
 167 +       .resource = cpmac_high_res_titan,
 168 +       .num_resources = ARRAY_SIZE(cpmac_high_res_titan),
 169 +};
 170 +
 171  static struct platform_device vlynq_low = {
 172         .id = 0,
 173         .name = "vlynq",
 174 @@ -291,6 +425,22 @@
 175         .num_resources = ARRAY_SIZE(vlynq_high_res),
 176  };
 177
 178 +static struct platform_device vlynq_low_titan = {
 179 +       .id = 0,
 180 +       .name = "vlynq",
 181 +       .dev.platform_data = &vlynq_low_data_titan,
 182 +       .resource = vlynq_low_res_titan,
 183 +       .num_resources = ARRAY_SIZE(vlynq_low_res_titan),
 184 +};
 185 +
 186 +static struct platform_device vlynq_high_titan = {
 187 +       .id = 1,
 188 +       .name = "vlynq",
 189 +       .dev.platform_data = &vlynq_high_data_titan,
 190 +       .resource = vlynq_high_res_titan,
 191 +       .num_resources = ARRAY_SIZE(vlynq_high_res_titan),
 192 +};
 193 +
 194
 195  static struct gpio_led default_leds[] = {
 196         {
 197 @@ -300,6 +450,11 @@
 198         },
 199  };
 200
 201 +static struct gpio_led titan_leds[] = {
 202 +       { .name = "status", .gpio = 8, .active_low = 1, },
 203 +       { .name = "wifi", .gpio = 13, .active_low = 1, },
 204 +};
 205 +
 206  static struct gpio_led dsl502t_leds[] = {
 207         {
 208                 .name = "status",
 209 @@ -496,6 +651,9 @@
 210         } else if (strstr(prid, "DG834")) {
 211                 ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
 212                 ar7_led_data.leds = dg834g_leds;
 213 +       } else if (strstr(prid, "CYWM")) {
 214 +               ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
 215 +               ar7_led_data.leds = titan_leds;
 216         }
 217  }
 218
 219 @@ -541,14 +699,18 @@
 220         if (res)
 221                 return res;
 222
 223 -       ar7_device_disable(vlynq_low_data.reset_bit);
 224 -       res = platform_device_register(&vlynq_low);
 225 +       ar7_device_disable(ar7_is_titan() ? vlynq_low_data_titan.reset_bit :
 226 +               vlynq_low_data.reset_bit);
 227 +       res = platform_device_register(ar7_is_titan() ? &vlynq_low_titan :
 228 +               &vlynq_low);
 229         if (res)
 230                 return res;
 231
 232         if (ar7_has_high_vlynq()) {
 233 -               ar7_device_disable(vlynq_high_data.reset_bit);
 234 -               res = platform_device_register(&vlynq_high);
 235 +               ar7_device_disable(ar7_is_titan() ? vlynq_high_data_titan.reset_bit :
 236 +                       vlynq_high_data.reset_bit);
 237 +               res = platform_device_register(ar7_is_titan() ? &vlynq_high_titan :
 238 +                       &vlynq_high);
 239                 if (res)
 240                         return res;
 241         }
 242 Index: linux-2.6.32.7/arch/mips/ar7/gpio.c
 243 ===================================================================
 244 --- linux-2.6.32.7.orig/arch/mips/ar7/gpio.c    2010-01-29 00:06:20.000000000 +0100
 245 +++ linux-2.6.32.7/arch/mips/ar7/gpio.c 2010-02-04 14:33:24.000000000 +0100
 246 @@ -21,11 +21,11 @@
 247
 248  #include <asm/mach-ar7/gpio.h>
 249
 250 -static const char *ar7_gpio_list[AR7_GPIO_MAX];
 251 +static const char *ar7_gpio_list[TITAN_GPIO_MAX];
 252
 253  int gpio_request(unsigned gpio, const char *label)
 254  {
 255 -       if (gpio >= AR7_GPIO_MAX)
 256 +       if (gpio >= (ar7_is_titan() ? TITAN_GPIO_MAX : AR7_GPIO_MAX))
 257                 return -EINVAL;
 258
 259         if (ar7_gpio_list[gpio])
 260 Index: linux-2.6.32.7/arch/mips/ar7/setup.c
 261 ===================================================================
 262 --- linux-2.6.32.7.orig/arch/mips/ar7/setup.c   2010-01-29 00:06:20.000000000 +0100
 263 +++ linux-2.6.32.7/arch/mips/ar7/setup.c        2010-02-04 14:33:24.000000000 +0100
 264 @@ -23,6 +23,9 @@
 265  #include <asm/reboot.h>
 266  #include <asm/mach-ar7/ar7.h>
 267  #include <asm/mach-ar7/prom.h>
 268 +#include <asm/mach-ar7/gpio.h>
 269 +
 270 +static int titan_variant;
 271
 272  static void ar7_machine_restart(char *command)
 273  {
 274 @@ -55,6 +58,18 @@
 275                 return "TI AR7 (TNETD7100)";
 276         case AR7_CHIP_7200:
 277                 return "TI AR7 (TNETD7200)";
 278 +       case AR7_CHIP_TITAN:
 279 +               titan_variant = ar7_init_titan_variant();
 280 +               switch (titan_variant /*(gpio_get_value_titan(1) >> 12) & 0xf*/) {
 281 +               case TITAN_CHIP_1050:
 282 +                       return "TI AR7 (TNETV1050)";
 283 +               case TITAN_CHIP_1055:
 284 +                       return "TI AR7 (TNETV1055)";
 285 +               case TITAN_CHIP_1056:
 286 +                       return "TI AR7 (TNETV1056)";
 287 +               case TITAN_CHIP_1060:
 288 +                       return "TI AR7 (TNETV1060)";
 289 +               }
 290         default:
 291                 return "TI AR7 (Unknown)";
 292         }
 293 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar7/ar7.h
 294 ===================================================================
 295 --- linux-2.6.32.7.orig/arch/mips/include/asm/mach-ar7/ar7.h    2010-01-29 00:06:20.000000000 +0100
 296 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar7/ar7.h 2010-02-04 14:33:24.000000000 +0100
 297 @@ -50,6 +50,11 @@
 298  #define UR8_REGS_WDT   (AR7_REGS_BASE + 0x0b00)
 299  #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
 300
 301 +#define TITAN_REGS_MAC0                (0x08640000)
 302 +#define TITAN_REGS_MAC1                (TITAN_REGS_MAC0 + 0x0800)
 303 +#define TITAN_REGS_VLYNQ0      (AR7_REGS_BASE + 0x1c00)
 304 +#define TITAN_REGS_VLYNQ1      (AR7_REGS_BASE + 0x1300)
 305 +
 306  #define AR7_RESET_PEREPHERIAL  0x0
 307  #define AR7_RESET_SOFTWARE     0x4
 308  #define AR7_RESET_STATUS       0x8
 309 @@ -59,15 +64,30 @@
 310  #define AR7_RESET_BIT_MDIO     22
 311  #define AR7_RESET_BIT_EPHY     26
 312
 313 +#define TITAN_RESET_BIT_EPHY1  28
 314 +
 315  /* GPIO control registers */
 316  #define AR7_GPIO_INPUT 0x0
 317  #define AR7_GPIO_OUTPUT        0x4
 318  #define AR7_GPIO_DIR   0x8
 319  #define AR7_GPIO_ENABLE        0xc
 320 +#define TITAN_GPIO_INPUT_0     0x0
 321 +#define TITAN_GPIO_INPUT_1     0x4
 322 +#define TITAN_GPIO_OUTPUT_0    0x8
 323 +#define TITAN_GPIO_OUTPUT_1    0xc
 324 +#define TITAN_GPIO_DIR_0       0x10
 325 +#define TITAN_GPIO_DIR_1       0x14
 326 +#define TITAN_GPIO_ENBL_0      0x18
 327 +#define TITAN_GPIO_ENBL_1      0x1c
 328
 329  #define AR7_CHIP_7100  0x18
 330  #define AR7_CHIP_7200  0x2b
 331  #define AR7_CHIP_7300  0x05
 332 +#define AR7_CHIP_TITAN 0x07
 333 +#define TITAN_CHIP_1050        0x0f
 334 +#define TITAN_CHIP_1055        0x0e
 335 +#define TITAN_CHIP_1056        0x0d
 336 +#define TITAN_CHIP_1060        0x07
 337
 338  /* Interrupts */
 339  #define AR7_IRQ_UART0  15
 340 @@ -95,14 +115,22 @@
 341
 342  extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
 343
 344 +static inline int ar7_is_titan(void)
 345 +{
 346 +       return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
 347 +               AR7_CHIP_TITAN;
 348 +}
 349 +
 350  static inline u16 ar7_chip_id(void)
 351  {
 352 -       return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
 353 +       return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
 354 +               KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
 355  }
 356
 357  static inline u8 ar7_chip_rev(void)
 358  {
 359 -       return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
 360 +       return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
 361 +               0x14))) >> 16) & 0xff;
 362  }
 363
 364  static inline int ar7_cpu_freq(void)
 365 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar7/gpio.h
 366 ===================================================================
 367 --- linux-2.6.32.7.orig/arch/mips/include/asm/mach-ar7/gpio.h   2010-01-29 00:06:20.000000000 +0100
 368 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar7/gpio.h        2010-02-04 14:39:21.000000000 +0100
 369 @@ -20,14 +20,18 @@
 370  #define __AR7_GPIO_H__
 371
 372  #include <asm/mach-ar7/ar7.h>
 373 +#ifndef __AR7_TITAN_H__
 374 +#include <asm/mach-ar7/titan.h>
 375 +#endif
 376
 377  #define AR7_GPIO_MAX 32
 378 +#define TITAN_GPIO_MAX 51
 379
 380  extern int gpio_request(unsigned gpio, const char *label);
 381  extern void gpio_free(unsigned gpio);
 382
 383  /* Common GPIO layer */
 384 -static inline int gpio_get_value(unsigned gpio)
 385 +static inline int gpio_get_value_ar7(unsigned gpio)
 386  {
 387         void __iomem *gpio_in =
 388                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT);
 389 @@ -35,7 +39,23 @@
 390         return readl(gpio_in) & (1 << gpio);
 391  }
 392
 393 -static inline void gpio_set_value(unsigned gpio, int value)
 394 +static inline int gpio_get_value_titan(unsigned gpio)
 395 +{
 396 +       void __iomem *gpio_in0 =
 397 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
 398 +       void __iomem *gpio_in1 =
 399 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_1);
 400 +
 401 +       return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
 402 +}
 403 +
 404 +static inline int gpio_get_value(unsigned gpio)
 405 +{
 406 +       return ar7_is_titan() ? gpio_get_value_titan(gpio) :
 407 +               gpio_get_value_ar7(gpio);
 408 +}
 409 +
 410 +static inline void gpio_set_value_ar7(unsigned gpio, int value)
 411  {
 412         void __iomem *gpio_out =
 413                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT);
 414 @@ -47,7 +67,29 @@
 415         writel(tmp, gpio_out);
 416  }
 417
 418 -static inline int gpio_direction_input(unsigned gpio)
 419 +static inline void gpio_set_value_titan(unsigned gpio, int value)
 420 +{
 421 +       void __iomem *gpio_out0 =
 422 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_0);
 423 +       void __iomem *gpio_out1 =
 424 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_1);
 425 +       unsigned tmp;
 426 +
 427 +       tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
 428 +       if (value)
 429 +               tmp |= 1 << (gpio & 0x1f);
 430 +       writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
 431 +}
 432 +
 433 +static inline void gpio_set_value(unsigned gpio, int value)
 434 +{
 435 +       if (ar7_is_titan())
 436 +               gpio_set_value_titan(gpio, value);
 437 +       else
 438 +               gpio_set_value_ar7(gpio, value);
 439 +}
 440 +
 441 +static inline int gpio_direction_input_ar7(unsigned gpio)
 442  {
 443         void __iomem *gpio_dir =
 444                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
 445 @@ -60,7 +102,29 @@
 446         return 0;
 447  }
 448
 449 -static inline int gpio_direction_output(unsigned gpio, int value)
 450 +static inline int gpio_direction_input_titan(unsigned gpio)
 451 +{
 452 +       void __iomem *gpio_dir0 =
 453 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0);
 454 +       void __iomem *gpio_dir1 =
 455 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1);
 456 +
 457 +       if (gpio >= TITAN_GPIO_MAX)
 458 +               return -EINVAL;
 459 +
 460 +       writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
 461 +               gpio >> 5 ? gpio_dir1 : gpio_dir0);
 462 +
 463 +       return 0;
 464 +}
 465 +
 466 +static inline int gpio_direction_input(unsigned gpio)
 467 +{
 468 +       return ar7_is_titan() ?  gpio_direction_input_titan(gpio) :
 469 +               gpio_direction_input_ar7(gpio);
 470 +}
 471 +
 472 +static inline int gpio_direction_output_ar7(unsigned gpio, int value)
 473  {
 474         void __iomem *gpio_dir =
 475                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
 476 @@ -74,6 +138,29 @@
 477         return 0;
 478  }
 479
 480 +static inline int gpio_direction_output_titan(unsigned gpio, int value)
 481 +{
 482 +       void __iomem *gpio_dir0 =
 483 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0);
 484 +       void __iomem *gpio_dir1 =
 485 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1);
 486 +
 487 +       if (gpio >= TITAN_GPIO_MAX)
 488 +               return -EINVAL;
 489 +
 490 +       gpio_set_value_titan(gpio, value);
 491 +       writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
 492 +               (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
 493 +
 494 +       return 0;
 495 +}
 496 +
 497 +static inline int gpio_direction_output(unsigned gpio, int value)
 498 +{
 499 +       return ar7_is_titan() ?  gpio_direction_output_titan(gpio, value) :
 500 +               gpio_direction_output_ar7(gpio, value);
 501 +}
 502 +
 503  static inline int gpio_to_irq(unsigned gpio)
 504  {
 505         return -EINVAL;
 506 @@ -85,7 +172,7 @@
 507  }
 508
 509  /* Board specific GPIO functions */
 510 -static inline int ar7_gpio_enable(unsigned gpio)
 511 +static inline int ar7_gpio_enable_ar7(unsigned gpio)
 512  {
 513         void __iomem *gpio_en =
 514                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
 515 @@ -95,7 +182,26 @@
 516         return 0;
 517  }
 518
 519 -static inline int ar7_gpio_disable(unsigned gpio)
 520 +static inline int ar7_gpio_enable_titan(unsigned gpio)
 521 +{
 522 +       void __iomem *gpio_en0 =
 523 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0);
 524 +       void __iomem *gpio_en1 =
 525 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1);
 526 +
 527 +       writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
 528 +               gpio >> 5 ? gpio_en1 : gpio_en0);
 529 +
 530 +       return 0;
 531 +}
 532 +
 533 +static inline int ar7_gpio_enable(unsigned gpio)
 534 +{
 535 +       return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
 536 +               ar7_gpio_enable_ar7(gpio);
 537 +}
 538 +
 539 +static inline int ar7_gpio_disable_ar7(unsigned gpio)
 540  {
 541         void __iomem *gpio_en =
 542                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
 543 @@ -105,6 +211,60 @@
 544         return 0;
 545  }
 546
 547 +static inline int ar7_gpio_disable_titan(unsigned gpio)
 548 +{
 549 +       void __iomem *gpio_en0 =
 550 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0);
 551 +       void __iomem *gpio_en1 =
 552 +               (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1);
 553 +
 554 +       writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
 555 +               gpio >> 5 ? gpio_en1 : gpio_en0);
 556 +
 557 +       return 0;
 558 +}
 559 +
 560 +static inline int ar7_gpio_disable(unsigned gpio)
 561 +{
 562 +       return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
 563 +               ar7_gpio_disable_ar7(gpio);
 564 +}
 565 +
 566 +static inline int ar7_init_titan_variant(void)
 567 +{
 568 +       /*UINT32 new_val;*/
 569 +       unsigned new_val;
 570 +
 571 +       /* set GPIO 44 - 47 as input */
 572 +       /*PAL_sysGpioCtrl(const int, GPIO_PIN, GPIO_INPUT_PIN); */
 573 +       /*define titan_gpio_ctrl in titan.h*/
 574 +       titan_gpio_ctrl(44, GPIO_PIN, GPIO_INPUT_PIN);
 575 +       titan_gpio_ctrl(45, GPIO_PIN, GPIO_INPUT_PIN);
 576 +       titan_gpio_ctrl(46, GPIO_PIN, GPIO_INPUT_PIN);
 577 +       titan_gpio_ctrl(47, GPIO_PIN, GPIO_INPUT_PIN);
 578 +
 579 +       /* read GPIO to get Titan variant type */
 580 +       /*fix this*/
 581 +       titan_sysGpioInValue( &new_val, 1 );
 582 +
 583 +       new_val >>= 12;
 584 +       new_val &= 0x0f;
 585 +
 586 +       switch ( new_val )
 587 +       {
 588 +       case TITAN_CHIP_1050:
 589 +       case TITAN_CHIP_1055:
 590 +       case TITAN_CHIP_1056:
 591 +       case TITAN_CHIP_1060:
 592 +               return new_val;
 593 +
 594 +       default:
 595 +               break;
 596 +       }
 597 +       /* In case we get an invalid value, return the default Titan chip */
 598 +       return TITAN_CHIP_1050;
 599 +}
 600 +
 601  #include <asm-generic/gpio.h>
 602
 603  #endif
 604 Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar7/titan.h
 605 ===================================================================
 606 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 607 +++ linux-2.6.32.7/arch/mips/include/asm/mach-ar7/titan.h       2010-02-04 14:40:44.000000000 +0100
 608 @@ -0,0 +1,176 @@
 609 +/*
 610 + * Copyright (C) 2008 Stanley Pinchak <stanley_dot_pinchak_at_gmail_dot_com>
 611 + *
 612 + * This program is free software; you can redistribute it and/or modify
 613 + * it under the terms of the GNU General Public License as published by
 614 + * the Free Software Foundation; either version 2 of the License, or
 615 + * (at your option) any later version.
 616 + *
 617 + * This program is distributed in the hope that it will be useful,
 618 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 619 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 620 + * GNU General Public License for more details.
 621 + *
 622 + * You should have received a copy of the GNU General Public License
 623 + * along with this program; if not, write to the Free Software
 624 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 625 + */
 626 +#ifndef __AR7_TITAN_H__
 627 +#define __AR7_TITAN_H__
 628 +
 629 +#include <asm/mach-ar7/gpio.h>
 630 +
 631 +typedef enum TITAN_GPIO_PIN_MODE_tag
 632 +{
 633 +    FUNCTIONAL_PIN = 0,
 634 +    GPIO_PIN = 1
 635 +} TITAN_GPIO_PIN_MODE_T;
 636 +
 637 +typedef enum TITAN_GPIO_PIN_DIRECTION_tag
 638 +{
 639 +    GPIO_OUTPUT_PIN = 0,
 640 +    GPIO_INPUT_PIN = 1
 641 +} TITAN_GPIO_PIN_DIRECTION_T;
 642 +
 643 +/**********************************************************************
 644 + *  GPIO Control
 645 + **********************************************************************/
 646 +
 647 +typedef struct
 648 +{
 649 +    int pinSelReg;
 650 +    int shift;
 651 +    int func;
 652 +
 653 +} GPIO_CFG;
 654 +
 655 +static GPIO_CFG gptable[]= {
 656 +                     /* PIN_SEL_REG, START_BIT, GPIO_CFG_MUX_VALUE */
 657 +                     {4,24,1},
 658 +                     {4,26,1},
 659 +                     {4,28,1},
 660 +                     {4,30,1},
 661 +                     {5,6,1},
 662 +                     {5,8,1},
 663 +                     {5,10,1},
 664 +                     {5,12,1},
 665 +                     {7,14,3},
 666 +                     {7,16,3},
 667 +                     {7,18,3},
 668 +                     {7,20,3},
 669 +                     {7,22,3},
 670 +                     {7,26,3},
 671 +                     {7,28,3},
 672 +                     {7,30,3},
 673 +                      {8,0,3},
 674 +                     {8,2,3},
 675 +                     {8,4,3},
 676 +                     {8,10,3},
 677 +                     {8,14,3},
 678 +                     {8,16,3},
 679 +                     {8,18,3},
 680 +                     {8,20,3},
 681 +                     {9,8,3},
 682 +                     {9,10,3},
 683 +                     {9,12,3},
 684 +                     {9,14,3},
 685 +                     {9,18,3},
 686 +                     {9,20,3},
 687 +                     {9,24,3},
 688 +                     {9,26,3},
 689 +                     {9,28,3},
 690 +                     {9,30,3},
 691 +                     {10,0,3},
 692 +                     {10,2,3},
 693 +                     {10,8,3},
 694 +                     {10,10,3},
 695 +                     {10,12,3},
 696 +                     {10,14,3},
 697 +                     {13,12,3},
 698 +                     {13,14,3},
 699 +                     {13,16,3},
 700 +                     {13,18,3},
 701 +                     {13,24,3},
 702 +                     {13,26,3},
 703 +                     {13,28,3},
 704 +                     {13,30,3},
 705 +                     {14,2,3},
 706 +                     {14,6,3},
 707 +                     {14,8,3},
 708 +                     {14,12,3}
 709 +};
 710 +
 711 +typedef struct
 712 +{
 713 +    volatile unsigned int reg[21];
 714 +}
 715 +PIN_SEL_REG_ARRAY_T;
 716 +
 717 +typedef struct
 718 +{
 719 +    unsigned int data_in [2];
 720 +    unsigned int data_out[2];
 721 +    unsigned int dir[2];
 722 +    unsigned int enable[2];
 723 +
 724 +} TITAN_GPIO_CONTROL_T;
 725 +
 726 +#define AVALANCHE_PIN_SEL_BASE        0xA861160C /*replace with KSEG1ADDR()*/
 727 +
 728 +static inline int titan_gpio_ctrl(unsigned int gpio_pin, TITAN_GPIO_PIN_MODE_T pin_mode,
 729 +                        TITAN_GPIO_PIN_DIRECTION_T pin_direction)
 730 +{
 731 +    int reg_index = 0;
 732 +    int mux_status;
 733 +    GPIO_CFG  gpio_cfg;
 734 +    volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE;
 735 +    volatile TITAN_GPIO_CONTROL_T   *gpio_cntl     = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
 736 +
 737 +    if (gpio_pin > 51 )
 738 +        return(-1);
 739 +
 740 +    gpio_cfg = gptable[gpio_pin];
 741 +    mux_status = (pin_sel_array->reg[gpio_cfg.pinSelReg - 1] >> gpio_cfg.shift) & 0x3;
 742 +    if(!((mux_status == 0 /* tri-stated */ ) || (mux_status == gpio_cfg.func /*GPIO functionality*/)))
 743 +    {
 744 +        return(-1); /* Pin have been configured for non GPIO funcs. */
 745 +    }
 746 +
 747 +    /* Set the pin to be used as GPIO. */
 748 +    pin_sel_array->reg[gpio_cfg.pinSelReg - 1] |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
 749 +
 750 +    /* Check whether gpio refers to the first GPIO reg or second. */
 751 +    if(gpio_pin > 31)
 752 +    {
 753 +       reg_index = 1;
 754 +       gpio_pin -= 32;
 755 +    }
 756 +
 757 +    if(pin_mode)
 758 +        gpio_cntl->enable[reg_index] |=  (1 << gpio_pin); /* Enable */
 759 +    else
 760 +       gpio_cntl->enable[reg_index] &= ~(1 << gpio_pin);
 761 +
 762 +    if(pin_direction)
 763 +        gpio_cntl->dir[reg_index] |=  (1 << gpio_pin); /* Input */
 764 +    else
 765 +       gpio_cntl->dir[reg_index] &= ~(1 << gpio_pin);
 766 +
 767 +    return(0);
 768 +
 769 +}/* end of function titan_gpio_ctrl */
 770 +
 771 +static inline int titan_sysGpioInValue(unsigned int *in_val, unsigned int reg_index)
 772 +{
 773 +    volatile TITAN_GPIO_CONTROL_T   *gpio_cntl     = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
 774 +
 775 +    if(reg_index > 1)
 776 +       return (-1);
 777 +
 778 +    *in_val = gpio_cntl->data_in[reg_index];
 779 +
 780 +    return (0);
 781 +}
 782 +
 783 +
 784 +#endif