[ar71xx] rename RouterStation stuff, and add machine type for the LSX board
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files-2.6.28 / arch / mips / include / asm / mach-ar71xx / ar71xx.h
1 /*
2 * Atheros AR71xx SoC specific definitions
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __ASM_MACH_AR71XX_H
15 #define __ASM_MACH_AR71XX_H
16
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/bitops.h>
21
22 #ifndef __ASSEMBLER__
23
24 #define AR71XX_PCI_MEM_BASE 0x10000000
25 #define AR71XX_PCI_MEM_SIZE 0x08000000
26 #define AR71XX_APB_BASE 0x18000000
27 #define AR71XX_GE0_BASE 0x19000000
28 #define AR71XX_GE0_SIZE 0x01000000
29 #define AR71XX_GE1_BASE 0x1a000000
30 #define AR71XX_GE1_SIZE 0x01000000
31 #define AR71XX_EHCI_BASE 0x1b000000
32 #define AR71XX_EHCI_SIZE 0x01000000
33 #define AR71XX_OHCI_BASE 0x1c000000
34 #define AR71XX_OHCI_SIZE 0x01000000
35 #define AR71XX_SPI_BASE 0x1f000000
36 #define AR71XX_SPI_SIZE 0x01000000
37
38 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
39 #define AR71XX_DDR_CTRL_SIZE 0x10000
40 #define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
41 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
42 #define AR71XX_UART_SIZE 0x10000
43 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
44 #define AR71XX_USB_CTRL_SIZE 0x10000
45 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
46 #define AR71XX_GPIO_SIZE 0x10000
47 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
48 #define AR71XX_PLL_SIZE 0x10000
49 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
50 #define AR71XX_RESET_SIZE 0x10000
51 #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
52 #define AR71XX_MII_SIZE 0x10000
53 #define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
54 #define AR71XX_SLIC_SIZE 0x10000
55 #define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
56 #define AR71XX_DMA_SIZE 0x10000
57 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
58 #define AR71XX_STEREO_SIZE 0x10000
59
60 #define AR71XX_CPU_IRQ_BASE 0
61 #define AR71XX_MISC_IRQ_BASE 8
62 #define AR71XX_MISC_IRQ_COUNT 8
63 #define AR71XX_GPIO_IRQ_BASE 16
64 #define AR71XX_GPIO_IRQ_COUNT 16
65 #define AR71XX_PCI_IRQ_BASE 32
66 #define AR71XX_PCI_IRQ_COUNT 4
67
68 #define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2)
69 #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
70 #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
71 #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
72 #define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
73 #define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
74
75 #define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
76 #define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
77 #define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
78 #define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
79 #define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
80 #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
81 #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
82 #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
83
84 #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
85
86 #define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
87 #define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
88 #define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
89 #define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 3)
90
91 extern u32 ar71xx_ahb_freq;
92 extern u32 ar71xx_cpu_freq;
93 extern u32 ar71xx_ddr_freq;
94
95 enum ar71xx_soc_type {
96 AR71XX_SOC_UNKNOWN,
97 AR71XX_SOC_AR7130,
98 AR71XX_SOC_AR7141,
99 AR71XX_SOC_AR7161,
100 AR71XX_SOC_AR9130,
101 AR71XX_SOC_AR9132
102 };
103
104 extern enum ar71xx_soc_type ar71xx_soc;
105
106 extern unsigned long ar71xx_mach_type;
107
108 #define AR71XX_MACH_GENERIC 0
109 #define AR71XX_MACH_WP543 1 /* Compex WP543 */
110 #define AR71XX_MACH_RB_411 2 /* MikroTik RouterBOARD 411/411A/411AH */
111 #define AR71XX_MACH_RB_433 3 /* MikroTik RouterBOARD 433/433AH */
112 #define AR71XX_MACH_RB_450 4 /* MikroTik RouterBOARD 450 */
113 #define AR71XX_MACH_RB_493 5 /* Mikrotik RouterBOARD 493/493AH */
114 #define AR71XX_MACH_AW_NR580 6 /* AzureWave AW-NR580 */
115 #define AR71XX_MACH_AP83 7 /* Atheros AP83 */
116 #define AR71XX_MACH_TEW_632BRP 8 /* TRENDnet TEW-632BRP */
117 #define AR71XX_MACH_UBNT_RS 9 /* Ubiquiti RouterStation */
118 #define AR71XX_MACH_UBNT_LSX 10 /* Ubiquiti LSX */
119
120 /*
121 * PLL block
122 */
123 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
124 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
125 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
126 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
127
128 #define AR71XX_PLL_DIV_SHIFT 3
129 #define AR71XX_PLL_DIV_MASK 0x1f
130 #define AR71XX_CPU_DIV_SHIFT 16
131 #define AR71XX_CPU_DIV_MASK 0x3
132 #define AR71XX_DDR_DIV_SHIFT 18
133 #define AR71XX_DDR_DIV_MASK 0x3
134 #define AR71XX_AHB_DIV_SHIFT 20
135 #define AR71XX_AHB_DIV_MASK 0x7
136
137 #define AR71XX_ETH0_PLL_SHIFT 17
138 #define AR71XX_ETH1_PLL_SHIFT 19
139
140 #define AR91XX_PLL_REG_CPU_CONFIG 0x00
141 #define AR91XX_PLL_REG_ETH_CONFIG 0x04
142 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
143 #define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
144
145 #define AR91XX_PLL_DIV_SHIFT 0
146 #define AR91XX_PLL_DIV_MASK 0x3ff
147 #define AR91XX_DDR_DIV_SHIFT 22
148 #define AR91XX_DDR_DIV_MASK 0x3
149 #define AR91XX_AHB_DIV_SHIFT 19
150 #define AR91XX_AHB_DIV_MASK 0x1
151
152 #define AR91XX_ETH0_PLL_SHIFT 20
153 #define AR91XX_ETH1_PLL_SHIFT 22
154
155 extern void __iomem *ar71xx_pll_base;
156
157 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
158 {
159 __raw_writel(val, ar71xx_pll_base + reg);
160 }
161
162 static inline u32 ar71xx_pll_rr(unsigned reg)
163 {
164 return __raw_readl(ar71xx_pll_base + reg);
165 }
166
167 /*
168 * USB_CONFIG block
169 */
170 #define USB_CTRL_REG_FLADJ 0x00
171 #define USB_CTRL_REG_CONFIG 0x04
172
173 extern void __iomem *ar71xx_usb_ctrl_base;
174
175 static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
176 {
177 __raw_writel(val, ar71xx_usb_ctrl_base + reg);
178 }
179
180 static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
181 {
182 return __raw_readl(ar71xx_usb_ctrl_base + reg);
183 }
184
185 extern void ar71xx_add_device_usb(void) __init;
186
187 /*
188 * GPIO block
189 */
190 #define GPIO_REG_OE 0x00
191 #define GPIO_REG_IN 0x04
192 #define GPIO_REG_OUT 0x08
193 #define GPIO_REG_SET 0x0c
194 #define GPIO_REG_CLEAR 0x10
195 #define GPIO_REG_INT_MODE 0x14
196 #define GPIO_REG_INT_TYPE 0x18
197 #define GPIO_REG_INT_POLARITY 0x1c
198 #define GPIO_REG_INT_PENDING 0x20
199 #define GPIO_REG_INT_ENABLE 0x24
200 #define GPIO_REG_FUNC 0x28
201
202 #define GPIO_FUNC_STEREO_EN BIT(17)
203 #define GPIO_FUNC_SLIC_EN BIT(16)
204 #define GPIO_FUNC_SPI_CS1_EN BIT(15)
205 #define GPIO_FUNC_SPI_CS0_EN BIT(14)
206 #define GPIO_FUNC_SPI_EN BIT(13)
207 #define GPIO_FUNC_UART_EN BIT(8)
208 #define GPIO_FUNC_USB_OC_EN BIT(4)
209 #define GPIO_FUNC_USB_CLK_EN BIT(0)
210
211 #define AR71XX_GPIO_COUNT 16
212 #define AR91XX_GPIO_COUNT 22
213
214 extern void __iomem *ar71xx_gpio_base;
215
216 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
217 {
218 __raw_writel(value, ar71xx_gpio_base + reg);
219 }
220
221 static inline u32 ar71xx_gpio_rr(unsigned reg)
222 {
223 return __raw_readl(ar71xx_gpio_base + reg);
224 }
225
226 extern void ar71xx_gpio_init(void) __init;
227 extern void ar71xx_gpio_function_enable(u32 mask);
228 extern void ar71xx_gpio_function_disable(u32 mask);
229
230 /*
231 * DDR_CTRL block
232 */
233 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
234 #define AR71XX_DDR_REG_PCI_WIN1 0x80
235 #define AR71XX_DDR_REG_PCI_WIN2 0x84
236 #define AR71XX_DDR_REG_PCI_WIN3 0x88
237 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
238 #define AR71XX_DDR_REG_PCI_WIN5 0x90
239 #define AR71XX_DDR_REG_PCI_WIN6 0x94
240 #define AR71XX_DDR_REG_PCI_WIN7 0x98
241 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
242 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
243 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
244 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
245
246 #define AR91XX_DDR_REG_FLUSH_GE0 0x7c
247 #define AR91XX_DDR_REG_FLUSH_GE1 0x80
248 #define AR91XX_DDR_REG_FLUSH_USB 0x84
249 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88
250
251 #define PCI_WIN0_OFFS 0x10000000
252 #define PCI_WIN1_OFFS 0x11000000
253 #define PCI_WIN2_OFFS 0x12000000
254 #define PCI_WIN3_OFFS 0x13000000
255 #define PCI_WIN4_OFFS 0x14000000
256 #define PCI_WIN5_OFFS 0x15000000
257 #define PCI_WIN6_OFFS 0x16000000
258 #define PCI_WIN7_OFFS 0x07000000
259
260 extern void __iomem *ar71xx_ddr_base;
261
262 static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
263 {
264 __raw_writel(val, ar71xx_ddr_base + reg);
265 }
266
267 static inline u32 ar71xx_ddr_rr(unsigned reg)
268 {
269 return __raw_readl(ar71xx_ddr_base + reg);
270 }
271
272 extern void ar71xx_ddr_flush(u32 reg);
273
274 /*
275 * PCI block
276 */
277 #define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
278 #define AR71XX_PCI_CFG_SIZE 0x100
279
280 #define PCI_REG_CRP_AD_CBE 0x00
281 #define PCI_REG_CRP_WRDATA 0x04
282 #define PCI_REG_CRP_RDDATA 0x08
283 #define PCI_REG_CFG_AD 0x0c
284 #define PCI_REG_CFG_CBE 0x10
285 #define PCI_REG_CFG_WRDATA 0x14
286 #define PCI_REG_CFG_RDDATA 0x18
287 #define PCI_REG_PCI_ERR 0x1c
288 #define PCI_REG_PCI_ERR_ADDR 0x20
289 #define PCI_REG_AHB_ERR 0x24
290 #define PCI_REG_AHB_ERR_ADDR 0x28
291
292 #define PCI_CRP_CMD_WRITE 0x00010000
293 #define PCI_CRP_CMD_READ 0x00000000
294 #define PCI_CFG_CMD_READ 0x0000000a
295 #define PCI_CFG_CMD_WRITE 0x0000000b
296
297 #define PCI_IDSEL_ADL_START 17
298
299 /*
300 * RESET block
301 */
302 #define AR71XX_RESET_REG_TIMER 0x00
303 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
304 #define AR71XX_RESET_REG_WDOG_CTRL 0x08
305 #define AR71XX_RESET_REG_WDOG 0x0c
306 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
307 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
308 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
309 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
310 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
311 #define AR71XX_RESET_REG_RESET_MODULE 0x24
312 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
313 #define AR71XX_RESET_REG_PERFC0 0x30
314 #define AR71XX_RESET_REG_PERFC1 0x34
315 #define AR71XX_RESET_REG_REV_ID 0x90
316
317 #define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
318 #define AR91XX_RESET_REG_RESET_MODULE 0x1c
319 #define AR91XX_RESET_REG_PERF_CTRL 0x20
320 #define AR91XX_RESET_REG_PERFC0 0x24
321 #define AR91XX_RESET_REG_PERFC1 0x28
322
323 #define WDOG_CTRL_LAST_RESET BIT(31)
324 #define WDOG_CTRL_ACTION_MASK 3
325 #define WDOG_CTRL_ACTION_NONE 0 /* no action */
326 #define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
327 #define WDOG_CTRL_ACTION_NMI 2 /* NMI */
328 #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
329
330 #define MISC_INT_DMA BIT(7)
331 #define MISC_INT_OHCI BIT(6)
332 #define MISC_INT_PERFC BIT(5)
333 #define MISC_INT_WDOG BIT(4)
334 #define MISC_INT_UART BIT(3)
335 #define MISC_INT_GPIO BIT(2)
336 #define MISC_INT_ERROR BIT(1)
337 #define MISC_INT_TIMER BIT(0)
338
339 #define PCI_INT_CORE BIT(4)
340 #define PCI_INT_DEV2 BIT(2)
341 #define PCI_INT_DEV1 BIT(1)
342 #define PCI_INT_DEV0 BIT(0)
343
344 #define RESET_MODULE_EXTERNAL BIT(28)
345 #define RESET_MODULE_FULL_CHIP BIT(24)
346 #define RESET_MODULE_CPU_NMI BIT(21)
347 #define RESET_MODULE_CPU_COLD BIT(20)
348 #define RESET_MODULE_DMA BIT(19)
349 #define RESET_MODULE_SLIC BIT(18)
350 #define RESET_MODULE_STEREO BIT(17)
351 #define RESET_MODULE_DDR BIT(16)
352 #define RESET_MODULE_GE1_MAC BIT(13)
353 #define RESET_MODULE_GE1_PHY BIT(12)
354 #define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
355 #define RESET_MODULE_GE0_MAC BIT(9)
356 #define RESET_MODULE_GE0_PHY BIT(8)
357 #define RESET_MODULE_USB_OHCI_DLL BIT(6)
358 #define RESET_MODULE_USB_HOST BIT(5)
359 #define RESET_MODULE_USB_PHY BIT(4)
360 #define RESET_MODULE_PCI_BUS BIT(1)
361 #define RESET_MODULE_PCI_CORE BIT(0)
362
363 #define REV_ID_MASK 0xff
364 #define REV_ID_CHIP_MASK 0xf3
365 #define REV_ID_CHIP_AR7130 0xa0
366 #define REV_ID_CHIP_AR7141 0xa1
367 #define REV_ID_CHIP_AR7161 0xa2
368 #define REV_ID_CHIP_AR9130 0xb0
369 #define REV_ID_CHIP_AR9132 0xb1
370
371 #define REV_ID_REVISION_MASK 0x3
372 #define REV_ID_REVISION_SHIFT 2
373
374 extern void __iomem *ar71xx_reset_base;
375
376 static inline void ar71xx_reset_wr(unsigned reg, u32 val)
377 {
378 __raw_writel(val, ar71xx_reset_base + reg);
379 }
380
381 static inline u32 ar71xx_reset_rr(unsigned reg)
382 {
383 return __raw_readl(ar71xx_reset_base + reg);
384 }
385
386 extern void ar71xx_device_stop(u32 mask);
387 extern void ar71xx_device_start(u32 mask);
388
389 /*
390 * SPI block
391 */
392 #define SPI_REG_FS 0x00 /* Function Select */
393 #define SPI_REG_CTRL 0x04 /* SPI Control */
394 #define SPI_REG_IOC 0x08 /* SPI I/O Control */
395 #define SPI_REG_RDS 0x0c /* Read Data Shift */
396
397 #define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
398
399 #define SPI_CTRL_RD BIT(6) /* Remap Disable */
400 #define SPI_CTRL_DIV_MASK 0x3f
401
402 #define SPI_IOC_DO BIT(0) /* Data Out pin */
403 #define SPI_IOC_CLK BIT(8) /* CLK pin */
404 #define SPI_IOC_CS(n) BIT(16 + (n))
405 #define SPI_IOC_CS0 SPI_IOC_CS(0)
406 #define SPI_IOC_CS1 SPI_IOC_CS(1)
407 #define SPI_IOC_CS2 SPI_IOC_CS(2)
408 #define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
409
410 /*
411 * MII_CTRL block
412 */
413 #define MII_REG_MII0_CTRL 0x00
414 #define MII_REG_MII1_CTRL 0x04
415
416 #define MII0_CTRL_IF_GMII 0
417 #define MII0_CTRL_IF_MII 1
418 #define MII0_CTRL_IF_RGMII 2
419 #define MII0_CTRL_IF_RMII 3
420
421 #define MII1_CTRL_IF_RGMII 0
422 #define MII1_CTRL_IF_RMII 1
423
424 #endif /* __ASSEMBLER__ */
425
426 #endif /* __ASM_MACH_AR71XX_H */