[ar71xx] fix handling of invalid arguments passed by some bootloaders (thanks to...
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files-2.6.28 / arch / mips / include / asm / mach-ar71xx / ar71xx.h
1 /*
2 * Atheros AR71xx SoC specific definitions
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __ASM_MACH_AR71XX_H
15 #define __ASM_MACH_AR71XX_H
16
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/bitops.h>
21
22 #ifndef __ASSEMBLER__
23
24 #define AR71XX_PCI_MEM_BASE 0x10000000
25 #define AR71XX_PCI_MEM_SIZE 0x08000000
26 #define AR71XX_APB_BASE 0x18000000
27 #define AR71XX_GE0_BASE 0x19000000
28 #define AR71XX_GE0_SIZE 0x01000000
29 #define AR71XX_GE1_BASE 0x1a000000
30 #define AR71XX_GE1_SIZE 0x01000000
31 #define AR71XX_EHCI_BASE 0x1b000000
32 #define AR71XX_EHCI_SIZE 0x01000000
33 #define AR71XX_OHCI_BASE 0x1c000000
34 #define AR71XX_OHCI_SIZE 0x01000000
35 #define AR71XX_SPI_BASE 0x1f000000
36 #define AR71XX_SPI_SIZE 0x01000000
37
38 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
39 #define AR71XX_DDR_CTRL_SIZE 0x10000
40 #define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
41 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
42 #define AR71XX_UART_SIZE 0x10000
43 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
44 #define AR71XX_USB_CTRL_SIZE 0x10000
45 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
46 #define AR71XX_GPIO_SIZE 0x10000
47 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
48 #define AR71XX_PLL_SIZE 0x10000
49 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
50 #define AR71XX_RESET_SIZE 0x10000
51 #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
52 #define AR71XX_MII_SIZE 0x10000
53 #define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
54 #define AR71XX_SLIC_SIZE 0x10000
55 #define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
56 #define AR71XX_DMA_SIZE 0x10000
57 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
58 #define AR71XX_STEREO_SIZE 0x10000
59 #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
60 #define AR91XX_WMAC_SIZE 0x30000
61
62 #define AR71XX_MEM_SIZE_MIN 0x0200000
63 #define AR71XX_MEM_SIZE_MAX 0x8000000
64
65 #define AR71XX_CPU_IRQ_BASE 0
66 #define AR71XX_MISC_IRQ_BASE 8
67 #define AR71XX_MISC_IRQ_COUNT 8
68 #define AR71XX_GPIO_IRQ_BASE 16
69 #define AR71XX_GPIO_IRQ_COUNT 16
70 #define AR71XX_PCI_IRQ_BASE 32
71 #define AR71XX_PCI_IRQ_COUNT 4
72
73 #define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2)
74 #define AR71XX_CPU_IRQ_WMAC (AR71XX_CPU_IRQ_BASE + 2)
75 #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
76 #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
77 #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
78 #define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
79 #define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
80
81 #define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
82 #define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
83 #define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
84 #define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
85 #define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
86 #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
87 #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
88 #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
89
90 #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
91
92 #define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
93 #define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
94 #define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
95 #define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 3)
96
97 extern u32 ar71xx_ahb_freq;
98 extern u32 ar71xx_cpu_freq;
99 extern u32 ar71xx_ddr_freq;
100
101 enum ar71xx_soc_type {
102 AR71XX_SOC_UNKNOWN,
103 AR71XX_SOC_AR7130,
104 AR71XX_SOC_AR7141,
105 AR71XX_SOC_AR7161,
106 AR71XX_SOC_AR9130,
107 AR71XX_SOC_AR9132
108 };
109
110 extern enum ar71xx_soc_type ar71xx_soc;
111
112 extern unsigned long ar71xx_mach_type;
113
114 #define AR71XX_MACH_GENERIC 0
115 #define AR71XX_MACH_WP543 1 /* Compex WP543 */
116 #define AR71XX_MACH_RB_411 2 /* MikroTik RouterBOARD 411/411A/411AH */
117 #define AR71XX_MACH_RB_433 3 /* MikroTik RouterBOARD 433/433AH */
118 #define AR71XX_MACH_RB_450 4 /* MikroTik RouterBOARD 450 */
119 #define AR71XX_MACH_RB_493 5 /* Mikrotik RouterBOARD 493/493AH */
120 #define AR71XX_MACH_AW_NR580 6 /* AzureWave AW-NR580 */
121 #define AR71XX_MACH_AP83 7 /* Atheros AP83 */
122 #define AR71XX_MACH_TEW_632BRP 8 /* TRENDnet TEW-632BRP */
123 #define AR71XX_MACH_UBNT_RS 9 /* Ubiquiti RouterStation */
124 #define AR71XX_MACH_UBNT_LSX 10 /* Ubiquiti LSX */
125 #define AR71XX_MACH_WNR2000 11 /* NETGEAR WNR2000 */
126 #define AR71XX_MACH_PB42 12 /* Atheros PB42 */
127 #define AR71XX_MACH_MZK_W300NH 13 /* Planex MZK-W300NH */
128 #define AR71XX_MACH_MZK_W04NU 14 /* Planex MZK-W04NU */
129
130 /*
131 * PLL block
132 */
133 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
134 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
135 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
136 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
137
138 #define AR71XX_PLL_DIV_SHIFT 3
139 #define AR71XX_PLL_DIV_MASK 0x1f
140 #define AR71XX_CPU_DIV_SHIFT 16
141 #define AR71XX_CPU_DIV_MASK 0x3
142 #define AR71XX_DDR_DIV_SHIFT 18
143 #define AR71XX_DDR_DIV_MASK 0x3
144 #define AR71XX_AHB_DIV_SHIFT 20
145 #define AR71XX_AHB_DIV_MASK 0x7
146
147 #define AR71XX_ETH0_PLL_SHIFT 17
148 #define AR71XX_ETH1_PLL_SHIFT 19
149
150 #define AR91XX_PLL_REG_CPU_CONFIG 0x00
151 #define AR91XX_PLL_REG_ETH_CONFIG 0x04
152 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
153 #define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
154
155 #define AR91XX_PLL_DIV_SHIFT 0
156 #define AR91XX_PLL_DIV_MASK 0x3ff
157 #define AR91XX_DDR_DIV_SHIFT 22
158 #define AR91XX_DDR_DIV_MASK 0x3
159 #define AR91XX_AHB_DIV_SHIFT 19
160 #define AR91XX_AHB_DIV_MASK 0x1
161
162 #define AR91XX_ETH0_PLL_SHIFT 20
163 #define AR91XX_ETH1_PLL_SHIFT 22
164
165 extern void __iomem *ar71xx_pll_base;
166
167 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
168 {
169 __raw_writel(val, ar71xx_pll_base + reg);
170 }
171
172 static inline u32 ar71xx_pll_rr(unsigned reg)
173 {
174 return __raw_readl(ar71xx_pll_base + reg);
175 }
176
177 /*
178 * USB_CONFIG block
179 */
180 #define USB_CTRL_REG_FLADJ 0x00
181 #define USB_CTRL_REG_CONFIG 0x04
182
183 extern void __iomem *ar71xx_usb_ctrl_base;
184
185 static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
186 {
187 __raw_writel(val, ar71xx_usb_ctrl_base + reg);
188 }
189
190 static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
191 {
192 return __raw_readl(ar71xx_usb_ctrl_base + reg);
193 }
194
195 extern void ar71xx_add_device_usb(void) __init;
196
197 /*
198 * GPIO block
199 */
200 #define GPIO_REG_OE 0x00
201 #define GPIO_REG_IN 0x04
202 #define GPIO_REG_OUT 0x08
203 #define GPIO_REG_SET 0x0c
204 #define GPIO_REG_CLEAR 0x10
205 #define GPIO_REG_INT_MODE 0x14
206 #define GPIO_REG_INT_TYPE 0x18
207 #define GPIO_REG_INT_POLARITY 0x1c
208 #define GPIO_REG_INT_PENDING 0x20
209 #define GPIO_REG_INT_ENABLE 0x24
210 #define GPIO_REG_FUNC 0x28
211
212 #define GPIO_FUNC_STEREO_EN BIT(17)
213 #define GPIO_FUNC_SLIC_EN BIT(16)
214 #define GPIO_FUNC_SPI_CS2_EN BIT(13)
215 #define GPIO_FUNC_SPI_CS1_EN BIT(12)
216 #define GPIO_FUNC_UART_EN BIT(8)
217 #define GPIO_FUNC_USB_OC_EN BIT(4)
218 #define GPIO_FUNC_USB_CLK_EN BIT(0)
219
220 #define AR71XX_GPIO_COUNT 16
221 #define AR91XX_GPIO_COUNT 22
222
223 extern void __iomem *ar71xx_gpio_base;
224
225 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
226 {
227 __raw_writel(value, ar71xx_gpio_base + reg);
228 }
229
230 static inline u32 ar71xx_gpio_rr(unsigned reg)
231 {
232 return __raw_readl(ar71xx_gpio_base + reg);
233 }
234
235 extern void ar71xx_gpio_init(void) __init;
236 extern void ar71xx_gpio_function_enable(u32 mask);
237 extern void ar71xx_gpio_function_disable(u32 mask);
238
239 /*
240 * DDR_CTRL block
241 */
242 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
243 #define AR71XX_DDR_REG_PCI_WIN1 0x80
244 #define AR71XX_DDR_REG_PCI_WIN2 0x84
245 #define AR71XX_DDR_REG_PCI_WIN3 0x88
246 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
247 #define AR71XX_DDR_REG_PCI_WIN5 0x90
248 #define AR71XX_DDR_REG_PCI_WIN6 0x94
249 #define AR71XX_DDR_REG_PCI_WIN7 0x98
250 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
251 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
252 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
253 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
254
255 #define AR91XX_DDR_REG_FLUSH_GE0 0x7c
256 #define AR91XX_DDR_REG_FLUSH_GE1 0x80
257 #define AR91XX_DDR_REG_FLUSH_USB 0x84
258 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88
259
260 #define PCI_WIN0_OFFS 0x10000000
261 #define PCI_WIN1_OFFS 0x11000000
262 #define PCI_WIN2_OFFS 0x12000000
263 #define PCI_WIN3_OFFS 0x13000000
264 #define PCI_WIN4_OFFS 0x14000000
265 #define PCI_WIN5_OFFS 0x15000000
266 #define PCI_WIN6_OFFS 0x16000000
267 #define PCI_WIN7_OFFS 0x07000000
268
269 extern void __iomem *ar71xx_ddr_base;
270
271 static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
272 {
273 __raw_writel(val, ar71xx_ddr_base + reg);
274 }
275
276 static inline u32 ar71xx_ddr_rr(unsigned reg)
277 {
278 return __raw_readl(ar71xx_ddr_base + reg);
279 }
280
281 extern void ar71xx_ddr_flush(u32 reg);
282
283 /*
284 * PCI block
285 */
286 #define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
287 #define AR71XX_PCI_CFG_SIZE 0x100
288
289 #define PCI_REG_CRP_AD_CBE 0x00
290 #define PCI_REG_CRP_WRDATA 0x04
291 #define PCI_REG_CRP_RDDATA 0x08
292 #define PCI_REG_CFG_AD 0x0c
293 #define PCI_REG_CFG_CBE 0x10
294 #define PCI_REG_CFG_WRDATA 0x14
295 #define PCI_REG_CFG_RDDATA 0x18
296 #define PCI_REG_PCI_ERR 0x1c
297 #define PCI_REG_PCI_ERR_ADDR 0x20
298 #define PCI_REG_AHB_ERR 0x24
299 #define PCI_REG_AHB_ERR_ADDR 0x28
300
301 #define PCI_CRP_CMD_WRITE 0x00010000
302 #define PCI_CRP_CMD_READ 0x00000000
303 #define PCI_CFG_CMD_READ 0x0000000a
304 #define PCI_CFG_CMD_WRITE 0x0000000b
305
306 #define PCI_IDSEL_ADL_START 17
307
308 /*
309 * RESET block
310 */
311 #define AR71XX_RESET_REG_TIMER 0x00
312 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
313 #define AR71XX_RESET_REG_WDOG_CTRL 0x08
314 #define AR71XX_RESET_REG_WDOG 0x0c
315 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
316 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
317 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
318 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
319 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
320 #define AR71XX_RESET_REG_RESET_MODULE 0x24
321 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
322 #define AR71XX_RESET_REG_PERFC0 0x30
323 #define AR71XX_RESET_REG_PERFC1 0x34
324 #define AR71XX_RESET_REG_REV_ID 0x90
325
326 #define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
327 #define AR91XX_RESET_REG_RESET_MODULE 0x1c
328 #define AR91XX_RESET_REG_PERF_CTRL 0x20
329 #define AR91XX_RESET_REG_PERFC0 0x24
330 #define AR91XX_RESET_REG_PERFC1 0x28
331
332 #define WDOG_CTRL_LAST_RESET BIT(31)
333 #define WDOG_CTRL_ACTION_MASK 3
334 #define WDOG_CTRL_ACTION_NONE 0 /* no action */
335 #define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
336 #define WDOG_CTRL_ACTION_NMI 2 /* NMI */
337 #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
338
339 #define MISC_INT_DMA BIT(7)
340 #define MISC_INT_OHCI BIT(6)
341 #define MISC_INT_PERFC BIT(5)
342 #define MISC_INT_WDOG BIT(4)
343 #define MISC_INT_UART BIT(3)
344 #define MISC_INT_GPIO BIT(2)
345 #define MISC_INT_ERROR BIT(1)
346 #define MISC_INT_TIMER BIT(0)
347
348 #define PCI_INT_CORE BIT(4)
349 #define PCI_INT_DEV2 BIT(2)
350 #define PCI_INT_DEV1 BIT(1)
351 #define PCI_INT_DEV0 BIT(0)
352
353 #define RESET_MODULE_EXTERNAL BIT(28)
354 #define RESET_MODULE_FULL_CHIP BIT(24)
355 #define RESET_MODULE_AMBA2WMAC BIT(22)
356 #define RESET_MODULE_CPU_NMI BIT(21)
357 #define RESET_MODULE_CPU_COLD BIT(20)
358 #define RESET_MODULE_DMA BIT(19)
359 #define RESET_MODULE_SLIC BIT(18)
360 #define RESET_MODULE_STEREO BIT(17)
361 #define RESET_MODULE_DDR BIT(16)
362 #define RESET_MODULE_GE1_MAC BIT(13)
363 #define RESET_MODULE_GE1_PHY BIT(12)
364 #define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
365 #define RESET_MODULE_GE0_MAC BIT(9)
366 #define RESET_MODULE_GE0_PHY BIT(8)
367 #define RESET_MODULE_USB_OHCI_DLL BIT(6)
368 #define RESET_MODULE_USB_HOST BIT(5)
369 #define RESET_MODULE_USB_PHY BIT(4)
370 #define RESET_MODULE_PCI_BUS BIT(1)
371 #define RESET_MODULE_PCI_CORE BIT(0)
372
373 #define REV_ID_MASK 0xff
374 #define REV_ID_CHIP_MASK 0xf3
375 #define REV_ID_CHIP_AR7130 0xa0
376 #define REV_ID_CHIP_AR7141 0xa1
377 #define REV_ID_CHIP_AR7161 0xa2
378 #define REV_ID_CHIP_AR9130 0xb0
379 #define REV_ID_CHIP_AR9132 0xb1
380
381 #define REV_ID_REVISION_MASK 0x3
382 #define REV_ID_REVISION_SHIFT 2
383
384 extern void __iomem *ar71xx_reset_base;
385
386 static inline void ar71xx_reset_wr(unsigned reg, u32 val)
387 {
388 __raw_writel(val, ar71xx_reset_base + reg);
389 }
390
391 static inline u32 ar71xx_reset_rr(unsigned reg)
392 {
393 return __raw_readl(ar71xx_reset_base + reg);
394 }
395
396 extern void ar71xx_device_stop(u32 mask);
397 extern void ar71xx_device_start(u32 mask);
398
399 /*
400 * SPI block
401 */
402 #define SPI_REG_FS 0x00 /* Function Select */
403 #define SPI_REG_CTRL 0x04 /* SPI Control */
404 #define SPI_REG_IOC 0x08 /* SPI I/O Control */
405 #define SPI_REG_RDS 0x0c /* Read Data Shift */
406
407 #define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
408
409 #define SPI_CTRL_RD BIT(6) /* Remap Disable */
410 #define SPI_CTRL_DIV_MASK 0x3f
411
412 #define SPI_IOC_DO BIT(0) /* Data Out pin */
413 #define SPI_IOC_CLK BIT(8) /* CLK pin */
414 #define SPI_IOC_CS(n) BIT(16 + (n))
415 #define SPI_IOC_CS0 SPI_IOC_CS(0)
416 #define SPI_IOC_CS1 SPI_IOC_CS(1)
417 #define SPI_IOC_CS2 SPI_IOC_CS(2)
418 #define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
419
420 /*
421 * MII_CTRL block
422 */
423 #define MII_REG_MII0_CTRL 0x00
424 #define MII_REG_MII1_CTRL 0x04
425
426 #define MII0_CTRL_IF_GMII 0
427 #define MII0_CTRL_IF_MII 1
428 #define MII0_CTRL_IF_RGMII 2
429 #define MII0_CTRL_IF_RMII 3
430
431 #define MII1_CTRL_IF_RGMII 0
432 #define MII1_CTRL_IF_RMII 1
433
434 #endif /* __ASSEMBLER__ */
435
436 #endif /* __ASM_MACH_AR71XX_H */