ar71xx: move arch specific files to files-2.6.39
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files-2.6.39 / arch / mips / ar71xx / mach-db120.c
1 /*
2 * Atheros DB120 board (WASP SoC) support
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/partitions.h>
14 #include <linux/platform_device.h>
15
16 #include <asm/mach-ar71xx/ar71xx.h>
17
18 #include "machtype.h"
19 #include "devices.h"
20 #include "dev-m25p80.h"
21 #include "dev-gpio-buttons.h"
22 #include "dev-leds-gpio.h"
23 #include "dev-usb.h"
24 #include "dev-ar9xxx-wmac.h"
25 #include "dev-db120-pci.h"
26
27 #define DB120_GPIO_LED_USB 11
28 #define DB120_GPIO_LED_WLAN_5G 12
29 #define DB120_GPIO_LED_WLAN_2G 13
30 #define DB120_GPIO_LED_STATUS 14
31 #define DB120_GPIO_LED_WPS 15
32
33 #define DB120_GPIO_BTN_WPS 16
34
35 #define DB120_MAC0_OFFSET 0
36 #define DB120_MAC1_OFFSET 6
37 #define DB120_WMAC_CALDATA_OFFSET 0x1000
38 #define DB120_PCIE_CALDATA_OFFSET 0x5000
39
40 #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
41 #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
42
43 #ifdef CONFIG_MTD_PARTITIONS
44 static struct mtd_partition db120_partitions[] = {
45 {
46 .name = "u-boot",
47 .offset = 0,
48 .size = 0x040000,
49 .mask_flags = MTD_WRITEABLE,
50 }, {
51 .name = "u-boot-env",
52 .offset = 0x040000,
53 .size = 0x010000,
54 }, {
55 .name = "rootfs",
56 .offset = 0x050000,
57 .size = 0x630000,
58 }, {
59 .name = "uImage",
60 .offset = 0x680000,
61 .size = 0x160000,
62 }, {
63 .name = "NVRAM",
64 .offset = 0x7E0000,
65 .size = 0x010000,
66 }, {
67 .name = "ART",
68 .offset = 0x7F0000,
69 .size = 0x010000,
70 .mask_flags = MTD_WRITEABLE,
71 }
72 };
73 #endif /* CONFIG_MTD_PARTITIONS */
74
75 static struct flash_platform_data db120_flash_data = {
76 #ifdef CONFIG_MTD_PARTITIONS
77 .parts = db120_partitions,
78 .nr_parts = ARRAY_SIZE(db120_partitions),
79 #endif
80 };
81
82 static struct gpio_led db120_leds_gpio[] __initdata = {
83 {
84 .name = "db120:green:status",
85 .gpio = DB120_GPIO_LED_STATUS,
86 .active_low = 1,
87 }, {
88 .name = "db120:green:wps",
89 .gpio = DB120_GPIO_LED_WPS,
90 .active_low = 1,
91 }, {
92 .name = "db120:green:wlan-5g",
93 .gpio = DB120_GPIO_LED_WLAN_5G,
94 .active_low = 1,
95 }, {
96 .name = "db120:green:wlan-2g",
97 .gpio = DB120_GPIO_LED_WLAN_2G,
98 .active_low = 1,
99 }, {
100 .name = "db120:green:usb",
101 .gpio = DB120_GPIO_LED_USB,
102 .active_low = 1,
103 }
104 };
105
106 static struct gpio_keys_button db120_gpio_keys[] __initdata = {
107 {
108 .desc = "WPS button",
109 .type = EV_KEY,
110 .code = KEY_WPS_BUTTON,
111 .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
112 .gpio = DB120_GPIO_BTN_WPS,
113 .active_low = 1,
114 }
115 };
116
117 static void __init db120_gmac_setup(void)
118 {
119 void __iomem *base;
120 u32 t;
121
122 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
123
124 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
125 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
126 AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
127 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
128
129 iounmap(base);
130 }
131
132 static void __init db120_setup(void)
133 {
134 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
135
136 ar71xx_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
137
138 ar71xx_add_device_usb();
139
140 ar71xx_add_device_m25p80(&db120_flash_data);
141
142 ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
143 db120_leds_gpio);
144
145 ar71xx_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
146 ARRAY_SIZE(db120_gpio_keys),
147 db120_gpio_keys);
148
149 db120_gmac_setup();
150
151 ar71xx_add_device_mdio(0, 0x0);
152 ar71xx_add_device_mdio(1, 0x0);
153
154 ar71xx_init_mac(ar71xx_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
155 #if 0
156 /* GMAC0 is connected to an AR8327 switch */
157 ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
158 ar71xx_eth0_data.speed = SPEED_1000;
159 ar71xx_eth0_data.duplex = DUPLEX_FULL;
160 #else
161 /* GMAC0 is connected to PHY4 of the internal switch */
162 ar71xx_switch_data.phy4_mii_en = 1;
163
164 ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
165 ar71xx_eth0_data.phy_mask = BIT(4);
166 ar71xx_eth0_data.mii_bus_dev = &ar71xx_mdio1_device.dev;
167 #endif
168
169 ar71xx_add_device_eth(0);
170
171 /* GMAC1 is connected to the internal switch */
172 ar71xx_init_mac(ar71xx_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
173 ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
174 ar71xx_eth1_data.speed = SPEED_1000;
175 ar71xx_eth1_data.duplex = DUPLEX_FULL;
176
177 ar71xx_add_device_eth(1);
178
179 ar9xxx_add_device_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
180
181 db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
182 }
183
184 MIPS_MACHINE(AR71XX_MACH_DB120, "DB120", "Atheros DB120", db120_setup);