projects / openwrt / svn-archive / archive.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ar71xx: nuke 2.6.39 support
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files-3.2 / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs_cpu)
89 dma_free_coherent(NULL, ring->size * ring->desc_size,
90 ring->descs_cpu, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
94 {
95 int err;
96 int i;
97
98 ring->desc_size = sizeof(struct ag71xx_desc);
99 if (ring->desc_size % cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring, ring->desc_size,
102 roundup(ring->desc_size, cache_line_size()));
103 ring->desc_size = roundup(ring->desc_size, cache_line_size());
104 }
105
106 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
107 &ring->descs_dma, GFP_ATOMIC);
108 if (!ring->descs_cpu) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113
114 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
115 if (!ring->buf) {
116 err = -ENOMEM;
117 goto err;
118 }
119
120 for (i = 0; i < ring->size; i++) {
121 int idx = i * ring->desc_size;
122 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
123 DBG("ag71xx: ring %p, desc %d at %p\n",
124 ring, i, ring->buf[i].desc);
125 }
126
127 return 0;
128
129 err:
130 return err;
131 }
132
133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
134 {
135 struct ag71xx_ring *ring = &ag->tx_ring;
136 struct net_device *dev = ag->dev;
137
138 while (ring->curr != ring->dirty) {
139 u32 i = ring->dirty % ring->size;
140
141 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
142 ring->buf[i].desc->ctrl = 0;
143 dev->stats.tx_errors++;
144 }
145
146 if (ring->buf[i].skb)
147 dev_kfree_skb_any(ring->buf[i].skb);
148
149 ring->buf[i].skb = NULL;
150
151 ring->dirty++;
152 }
153
154 /* flush descriptors */
155 wmb();
156
157 }
158
159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
160 {
161 struct ag71xx_ring *ring = &ag->tx_ring;
162 int i;
163
164 for (i = 0; i < ring->size; i++) {
165 ring->buf[i].desc->next = (u32) (ring->descs_dma +
166 ring->desc_size * ((i + 1) % ring->size));
167
168 ring->buf[i].desc->ctrl = DESC_EMPTY;
169 ring->buf[i].skb = NULL;
170 }
171
172 /* flush descriptors */
173 wmb();
174
175 ring->curr = 0;
176 ring->dirty = 0;
177 }
178
179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 int i;
183
184 if (!ring->buf)
185 return;
186
187 for (i = 0; i < ring->size; i++)
188 if (ring->buf[i].skb) {
189 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
190 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
191 kfree_skb(ring->buf[i].skb);
192 }
193 }
194
195 static int ag71xx_rx_reserve(struct ag71xx *ag)
196 {
197 int reserve = 0;
198
199 if (ag71xx_get_pdata(ag)->is_ar724x) {
200 if (!ag71xx_has_ar8216(ag))
201 reserve = 2;
202
203 if (ag->phy_dev)
204 reserve += 4 - (ag->phy_dev->pkt_align % 4);
205
206 reserve %= 4;
207 }
208
209 return reserve + AG71XX_RX_PKT_RESERVE;
210 }
211
212
213 static int ag71xx_ring_rx_init(struct ag71xx *ag)
214 {
215 struct ag71xx_ring *ring = &ag->rx_ring;
216 unsigned int reserve = ag71xx_rx_reserve(ag);
217 unsigned int i;
218 int ret;
219
220 ret = 0;
221 for (i = 0; i < ring->size; i++) {
222 ring->buf[i].desc->next = (u32) (ring->descs_dma +
223 ring->desc_size * ((i + 1) % ring->size));
224
225 DBG("ag71xx: RX desc at %p, next is %08x\n",
226 ring->buf[i].desc,
227 ring->buf[i].desc->next);
228 }
229
230 for (i = 0; i < ring->size; i++) {
231 struct sk_buff *skb;
232 dma_addr_t dma_addr;
233
234 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
235 if (!skb) {
236 ret = -ENOMEM;
237 break;
238 }
239
240 skb->dev = ag->dev;
241 skb_reserve(skb, reserve);
242
243 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
244 AG71XX_RX_PKT_SIZE,
245 DMA_FROM_DEVICE);
246 ring->buf[i].skb = skb;
247 ring->buf[i].dma_addr = dma_addr;
248 ring->buf[i].desc->data = (u32) dma_addr;
249 ring->buf[i].desc->ctrl = DESC_EMPTY;
250 }
251
252 /* flush descriptors */
253 wmb();
254
255 ring->curr = 0;
256 ring->dirty = 0;
257
258 return ret;
259 }
260
261 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
262 {
263 struct ag71xx_ring *ring = &ag->rx_ring;
264 unsigned int reserve = ag71xx_rx_reserve(ag);
265 unsigned int count;
266
267 count = 0;
268 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
269 unsigned int i;
270
271 i = ring->dirty % ring->size;
272
273 if (ring->buf[i].skb == NULL) {
274 dma_addr_t dma_addr;
275 struct sk_buff *skb;
276
277 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
278 if (skb == NULL)
279 break;
280
281 skb_reserve(skb, reserve);
282 skb->dev = ag->dev;
283
284 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
285 AG71XX_RX_PKT_SIZE,
286 DMA_FROM_DEVICE);
287
288 ring->buf[i].skb = skb;
289 ring->buf[i].dma_addr = dma_addr;
290 ring->buf[i].desc->data = (u32) dma_addr;
291 }
292
293 ring->buf[i].desc->ctrl = DESC_EMPTY;
294 count++;
295 }
296
297 /* flush descriptors */
298 wmb();
299
300 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
301
302 return count;
303 }
304
305 static int ag71xx_rings_init(struct ag71xx *ag)
306 {
307 int ret;
308
309 ret = ag71xx_ring_alloc(&ag->tx_ring);
310 if (ret)
311 return ret;
312
313 ag71xx_ring_tx_init(ag);
314
315 ret = ag71xx_ring_alloc(&ag->rx_ring);
316 if (ret)
317 return ret;
318
319 ret = ag71xx_ring_rx_init(ag);
320 return ret;
321 }
322
323 static void ag71xx_rings_cleanup(struct ag71xx *ag)
324 {
325 ag71xx_ring_rx_clean(ag);
326 ag71xx_ring_free(&ag->rx_ring);
327
328 ag71xx_ring_tx_clean(ag);
329 ag71xx_ring_free(&ag->tx_ring);
330 }
331
332 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
333 {
334 switch (ag->speed) {
335 case SPEED_1000:
336 return "1000";
337 case SPEED_100:
338 return "100";
339 case SPEED_10:
340 return "10";
341 }
342
343 return "?";
344 }
345
346 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
347 {
348 u32 t;
349
350 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
351 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
352
353 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
354
355 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
356 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
357 }
358
359 static void ag71xx_dma_reset(struct ag71xx *ag)
360 {
361 u32 val;
362 int i;
363
364 ag71xx_dump_dma_regs(ag);
365
366 /* stop RX and TX */
367 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
368 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
369
370 /*
371 * give the hardware some time to really stop all rx/tx activity
372 * clearing the descriptors too early causes random memory corruption
373 */
374 mdelay(1);
375
376 /* clear descriptor addresses */
377 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
378 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
379
380 /* clear pending RX/TX interrupts */
381 for (i = 0; i < 256; i++) {
382 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
383 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
384 }
385
386 /* clear pending errors */
387 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
388 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
389
390 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
391 if (val)
392 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
393 ag->dev->name, val);
394
395 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
396
397 /* mask out reserved bits */
398 val &= ~0xff000000;
399
400 if (val)
401 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
402 ag->dev->name, val);
403
404 ag71xx_dump_dma_regs(ag);
405 }
406
407 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
408 MAC_CFG1_SRX | MAC_CFG1_STX)
409
410 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
411
412 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
413 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
414 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
415 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
416 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
417 FIFO_CFG4_VT)
418
419 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
420 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
421 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
422 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
423 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
424 FIFO_CFG5_17 | FIFO_CFG5_SF)
425
426 static void ag71xx_hw_stop(struct ag71xx *ag)
427 {
428 /* disable all interrupts and stop the rx/tx engine */
429 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
430 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
431 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
432 }
433
434 static void ag71xx_hw_setup(struct ag71xx *ag)
435 {
436 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
437
438 /* setup MAC configuration registers */
439 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
440
441 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
442 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
443
444 /* setup max frame length */
445 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
446
447 /* setup FIFO configuration registers */
448 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
449 if (pdata->is_ar724x) {
450 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
451 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
452 } else {
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
454 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
455 }
456 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
457 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
458 }
459
460 static void ag71xx_hw_init(struct ag71xx *ag)
461 {
462 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
463 u32 reset_mask = pdata->reset_bit;
464
465 ag71xx_hw_stop(ag);
466
467 if (pdata->is_ar724x) {
468 u32 reset_phy = reset_mask;
469
470 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
471 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
472
473 ath79_device_reset_set(reset_phy);
474 mdelay(50);
475 ath79_device_reset_clear(reset_phy);
476 mdelay(200);
477 }
478
479 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
480 udelay(20);
481
482 ath79_device_reset_set(reset_mask);
483 mdelay(100);
484 ath79_device_reset_clear(reset_mask);
485 mdelay(200);
486
487 ag71xx_hw_setup(ag);
488
489 ag71xx_dma_reset(ag);
490 }
491
492 static void ag71xx_fast_reset(struct ag71xx *ag)
493 {
494 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
495 struct net_device *dev = ag->dev;
496 u32 reset_mask = pdata->reset_bit;
497 u32 rx_ds, tx_ds;
498 u32 mii_reg;
499
500 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
501
502 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
503 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
504 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
505
506 ath79_device_reset_set(reset_mask);
507 udelay(10);
508 ath79_device_reset_clear(reset_mask);
509 udelay(10);
510
511 ag71xx_dma_reset(ag);
512 ag71xx_hw_setup(ag);
513
514 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
515 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
516 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
517
518 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
519 }
520
521 static void ag71xx_hw_start(struct ag71xx *ag)
522 {
523 /* start RX engine */
524 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
525
526 /* enable interrupts */
527 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
528 }
529
530 void ag71xx_link_adjust(struct ag71xx *ag)
531 {
532 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
533 u32 cfg2;
534 u32 ifctl;
535 u32 fifo5;
536
537 if (!ag->link) {
538 ag71xx_hw_stop(ag);
539 netif_carrier_off(ag->dev);
540 if (netif_msg_link(ag))
541 pr_info("%s: link down\n", ag->dev->name);
542 return;
543 }
544
545 if (pdata->is_ar724x)
546 ag71xx_fast_reset(ag);
547
548 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
549 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
550 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
551
552 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
553 ifctl &= ~(MAC_IFCTL_SPEED);
554
555 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
556 fifo5 &= ~FIFO_CFG5_BM;
557
558 switch (ag->speed) {
559 case SPEED_1000:
560 cfg2 |= MAC_CFG2_IF_1000;
561 fifo5 |= FIFO_CFG5_BM;
562 break;
563 case SPEED_100:
564 cfg2 |= MAC_CFG2_IF_10_100;
565 ifctl |= MAC_IFCTL_SPEED;
566 break;
567 case SPEED_10:
568 cfg2 |= MAC_CFG2_IF_10_100;
569 break;
570 default:
571 BUG();
572 return;
573 }
574
575 if (pdata->is_ar91xx)
576 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
577 else if (pdata->is_ar724x)
578 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
579 else
580 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
581
582 if (pdata->set_speed)
583 pdata->set_speed(ag->speed);
584
585 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
586 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
587 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
588 ag71xx_hw_start(ag);
589
590 netif_carrier_on(ag->dev);
591 if (netif_msg_link(ag))
592 pr_info("%s: link up (%sMbps/%s duplex)\n",
593 ag->dev->name,
594 ag71xx_speed_str(ag),
595 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
596
597 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
598 ag->dev->name,
599 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
600 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
601 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
602
603 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
604 ag->dev->name,
605 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
606 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
607 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
608
609 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
610 ag->dev->name,
611 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
612 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
613 }
614
615 static int ag71xx_open(struct net_device *dev)
616 {
617 struct ag71xx *ag = netdev_priv(dev);
618 int ret;
619
620 ret = ag71xx_rings_init(ag);
621 if (ret)
622 goto err;
623
624 napi_enable(&ag->napi);
625
626 netif_carrier_off(dev);
627 ag71xx_phy_start(ag);
628
629 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
630 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
631
632 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
633
634 netif_start_queue(dev);
635
636 return 0;
637
638 err:
639 ag71xx_rings_cleanup(ag);
640 return ret;
641 }
642
643 static int ag71xx_stop(struct net_device *dev)
644 {
645 struct ag71xx *ag = netdev_priv(dev);
646 unsigned long flags;
647
648 netif_carrier_off(dev);
649 ag71xx_phy_stop(ag);
650
651 spin_lock_irqsave(&ag->lock, flags);
652
653 netif_stop_queue(dev);
654
655 ag71xx_hw_stop(ag);
656 ag71xx_dma_reset(ag);
657
658 napi_disable(&ag->napi);
659 del_timer_sync(&ag->oom_timer);
660
661 spin_unlock_irqrestore(&ag->lock, flags);
662
663 ag71xx_rings_cleanup(ag);
664
665 return 0;
666 }
667
668 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
669 struct net_device *dev)
670 {
671 struct ag71xx *ag = netdev_priv(dev);
672 struct ag71xx_ring *ring = &ag->tx_ring;
673 struct ag71xx_desc *desc;
674 dma_addr_t dma_addr;
675 int i;
676
677 i = ring->curr % ring->size;
678 desc = ring->buf[i].desc;
679
680 if (!ag71xx_desc_empty(desc))
681 goto err_drop;
682
683 if (ag71xx_has_ar8216(ag))
684 ag71xx_add_ar8216_header(ag, skb);
685
686 if (skb->len <= 0) {
687 DBG("%s: packet len is too small\n", ag->dev->name);
688 goto err_drop;
689 }
690
691 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
692 DMA_TO_DEVICE);
693
694 ring->buf[i].skb = skb;
695 ring->buf[i].timestamp = jiffies;
696
697 /* setup descriptor fields */
698 desc->data = (u32) dma_addr;
699 desc->ctrl = (skb->len & DESC_PKTLEN_M);
700
701 /* flush descriptor */
702 wmb();
703
704 ring->curr++;
705 if (ring->curr == (ring->dirty + ring->size)) {
706 DBG("%s: tx queue full\n", ag->dev->name);
707 netif_stop_queue(dev);
708 }
709
710 DBG("%s: packet injected into TX queue\n", ag->dev->name);
711
712 /* enable TX engine */
713 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
714
715 return NETDEV_TX_OK;
716
717 err_drop:
718 dev->stats.tx_dropped++;
719
720 dev_kfree_skb(skb);
721 return NETDEV_TX_OK;
722 }
723
724 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
725 {
726 struct ag71xx *ag = netdev_priv(dev);
727 int ret;
728
729 switch (cmd) {
730 case SIOCETHTOOL:
731 if (ag->phy_dev == NULL)
732 break;
733
734 spin_lock_irq(&ag->lock);
735 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
736 spin_unlock_irq(&ag->lock);
737 return ret;
738
739 case SIOCSIFHWADDR:
740 if (copy_from_user
741 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
742 return -EFAULT;
743 return 0;
744
745 case SIOCGIFHWADDR:
746 if (copy_to_user
747 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
748 return -EFAULT;
749 return 0;
750
751 case SIOCGMIIPHY:
752 case SIOCGMIIREG:
753 case SIOCSMIIREG:
754 if (ag->phy_dev == NULL)
755 break;
756
757 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
758
759 default:
760 break;
761 }
762
763 return -EOPNOTSUPP;
764 }
765
766 static void ag71xx_oom_timer_handler(unsigned long data)
767 {
768 struct net_device *dev = (struct net_device *) data;
769 struct ag71xx *ag = netdev_priv(dev);
770
771 napi_schedule(&ag->napi);
772 }
773
774 static void ag71xx_tx_timeout(struct net_device *dev)
775 {
776 struct ag71xx *ag = netdev_priv(dev);
777
778 if (netif_msg_tx_err(ag))
779 pr_info("%s: tx timeout\n", ag->dev->name);
780
781 schedule_work(&ag->restart_work);
782 }
783
784 static void ag71xx_restart_work_func(struct work_struct *work)
785 {
786 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
787
788 if (ag71xx_get_pdata(ag)->is_ar724x) {
789 ag->link = 0;
790 ag71xx_link_adjust(ag);
791 return;
792 }
793
794 ag71xx_stop(ag->dev);
795 ag71xx_open(ag->dev);
796 }
797
798 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
799 {
800 u32 rx_sm, tx_sm, rx_fd;
801
802 if (likely(time_before(jiffies, timestamp + HZ/10)))
803 return false;
804
805 if (!netif_carrier_ok(ag->dev))
806 return false;
807
808 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
809 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
810 return true;
811
812 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
813 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
814 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
815 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
816 return true;
817
818 return false;
819 }
820
821 static int ag71xx_tx_packets(struct ag71xx *ag)
822 {
823 struct ag71xx_ring *ring = &ag->tx_ring;
824 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
825 int sent;
826
827 DBG("%s: processing TX ring\n", ag->dev->name);
828
829 sent = 0;
830 while (ring->dirty != ring->curr) {
831 unsigned int i = ring->dirty % ring->size;
832 struct ag71xx_desc *desc = ring->buf[i].desc;
833 struct sk_buff *skb = ring->buf[i].skb;
834
835 if (!ag71xx_desc_empty(desc)) {
836 if (pdata->is_ar7240 &&
837 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
838 schedule_work(&ag->restart_work);
839 break;
840 }
841
842 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
843
844 ag->dev->stats.tx_bytes += skb->len;
845 ag->dev->stats.tx_packets++;
846
847 dev_kfree_skb_any(skb);
848 ring->buf[i].skb = NULL;
849
850 ring->dirty++;
851 sent++;
852 }
853
854 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
855
856 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
857 netif_wake_queue(ag->dev);
858
859 return sent;
860 }
861
862 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
863 {
864 struct net_device *dev = ag->dev;
865 struct ag71xx_ring *ring = &ag->rx_ring;
866 int done = 0;
867
868 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
869 dev->name, limit, ring->curr, ring->dirty);
870
871 while (done < limit) {
872 unsigned int i = ring->curr % ring->size;
873 struct ag71xx_desc *desc = ring->buf[i].desc;
874 struct sk_buff *skb;
875 int pktlen;
876 int err = 0;
877
878 if (ag71xx_desc_empty(desc))
879 break;
880
881 if ((ring->dirty + ring->size) == ring->curr) {
882 ag71xx_assert(0);
883 break;
884 }
885
886 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
887
888 skb = ring->buf[i].skb;
889 pktlen = ag71xx_desc_pktlen(desc);
890 pktlen -= ETH_FCS_LEN;
891
892 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
893 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
894
895 dev->last_rx = jiffies;
896 dev->stats.rx_packets++;
897 dev->stats.rx_bytes += pktlen;
898
899 skb_put(skb, pktlen);
900 if (ag71xx_has_ar8216(ag))
901 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
902
903 if (err) {
904 dev->stats.rx_dropped++;
905 kfree_skb(skb);
906 } else {
907 skb->dev = dev;
908 skb->ip_summed = CHECKSUM_NONE;
909 if (ag->phy_dev) {
910 ag->phy_dev->netif_receive_skb(skb);
911 } else {
912 skb->protocol = eth_type_trans(skb, dev);
913 netif_receive_skb(skb);
914 }
915 }
916
917 ring->buf[i].skb = NULL;
918 done++;
919
920 ring->curr++;
921 }
922
923 ag71xx_ring_rx_refill(ag);
924
925 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
926 dev->name, ring->curr, ring->dirty, done);
927
928 return done;
929 }
930
931 static int ag71xx_poll(struct napi_struct *napi, int limit)
932 {
933 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
934 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
935 struct net_device *dev = ag->dev;
936 struct ag71xx_ring *rx_ring;
937 unsigned long flags;
938 u32 status;
939 int tx_done;
940 int rx_done;
941
942 pdata->ddr_flush();
943 tx_done = ag71xx_tx_packets(ag);
944
945 DBG("%s: processing RX ring\n", dev->name);
946 rx_done = ag71xx_rx_packets(ag, limit);
947
948 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
949
950 rx_ring = &ag->rx_ring;
951 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL)
952 goto oom;
953
954 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
955 if (unlikely(status & RX_STATUS_OF)) {
956 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
957 dev->stats.rx_fifo_errors++;
958
959 /* restart RX */
960 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
961 }
962
963 if (rx_done < limit) {
964 if (status & RX_STATUS_PR)
965 goto more;
966
967 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
968 if (status & TX_STATUS_PS)
969 goto more;
970
971 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
972 dev->name, rx_done, tx_done, limit);
973
974 napi_complete(napi);
975
976 /* enable interrupts */
977 spin_lock_irqsave(&ag->lock, flags);
978 ag71xx_int_enable(ag, AG71XX_INT_POLL);
979 spin_unlock_irqrestore(&ag->lock, flags);
980 return rx_done;
981 }
982
983 more:
984 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
985 dev->name, rx_done, tx_done, limit);
986 return rx_done;
987
988 oom:
989 if (netif_msg_rx_err(ag))
990 pr_info("%s: out of memory\n", dev->name);
991
992 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
993 napi_complete(napi);
994 return 0;
995 }
996
997 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
998 {
999 struct net_device *dev = dev_id;
1000 struct ag71xx *ag = netdev_priv(dev);
1001 u32 status;
1002
1003 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1004 ag71xx_dump_intr(ag, "raw", status);
1005
1006 if (unlikely(!status))
1007 return IRQ_NONE;
1008
1009 if (unlikely(status & AG71XX_INT_ERR)) {
1010 if (status & AG71XX_INT_TX_BE) {
1011 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1012 dev_err(&dev->dev, "TX BUS error\n");
1013 }
1014 if (status & AG71XX_INT_RX_BE) {
1015 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1016 dev_err(&dev->dev, "RX BUS error\n");
1017 }
1018 }
1019
1020 if (likely(status & AG71XX_INT_POLL)) {
1021 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1022 DBG("%s: enable polling mode\n", dev->name);
1023 napi_schedule(&ag->napi);
1024 }
1025
1026 ag71xx_debugfs_update_int_stats(ag, status);
1027
1028 return IRQ_HANDLED;
1029 }
1030
1031 #ifdef CONFIG_NET_POLL_CONTROLLER
1032 /*
1033 * Polling 'interrupt' - used by things like netconsole to send skbs
1034 * without having to re-enable interrupts. It's not called while
1035 * the interrupt routine is executing.
1036 */
1037 static void ag71xx_netpoll(struct net_device *dev)
1038 {
1039 disable_irq(dev->irq);
1040 ag71xx_interrupt(dev->irq, dev);
1041 enable_irq(dev->irq);
1042 }
1043 #endif
1044
1045 static const struct net_device_ops ag71xx_netdev_ops = {
1046 .ndo_open = ag71xx_open,
1047 .ndo_stop = ag71xx_stop,
1048 .ndo_start_xmit = ag71xx_hard_start_xmit,
1049 .ndo_do_ioctl = ag71xx_do_ioctl,
1050 .ndo_tx_timeout = ag71xx_tx_timeout,
1051 .ndo_change_mtu = eth_change_mtu,
1052 .ndo_set_mac_address = eth_mac_addr,
1053 .ndo_validate_addr = eth_validate_addr,
1054 #ifdef CONFIG_NET_POLL_CONTROLLER
1055 .ndo_poll_controller = ag71xx_netpoll,
1056 #endif
1057 };
1058
1059 static int __devinit ag71xx_probe(struct platform_device *pdev)
1060 {
1061 struct net_device *dev;
1062 struct resource *res;
1063 struct ag71xx *ag;
1064 struct ag71xx_platform_data *pdata;
1065 int err;
1066
1067 pdata = pdev->dev.platform_data;
1068 if (!pdata) {
1069 dev_err(&pdev->dev, "no platform data specified\n");
1070 err = -ENXIO;
1071 goto err_out;
1072 }
1073
1074 if (pdata->mii_bus_dev == NULL) {
1075 dev_err(&pdev->dev, "no MII bus device specified\n");
1076 err = -EINVAL;
1077 goto err_out;
1078 }
1079
1080 dev = alloc_etherdev(sizeof(*ag));
1081 if (!dev) {
1082 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1083 err = -ENOMEM;
1084 goto err_out;
1085 }
1086
1087 SET_NETDEV_DEV(dev, &pdev->dev);
1088
1089 ag = netdev_priv(dev);
1090 ag->pdev = pdev;
1091 ag->dev = dev;
1092 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1093 AG71XX_DEFAULT_MSG_ENABLE);
1094 spin_lock_init(&ag->lock);
1095
1096 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1097 if (!res) {
1098 dev_err(&pdev->dev, "no mac_base resource found\n");
1099 err = -ENXIO;
1100 goto err_out;
1101 }
1102
1103 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1104 if (!ag->mac_base) {
1105 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1106 err = -ENOMEM;
1107 goto err_free_dev;
1108 }
1109
1110 dev->irq = platform_get_irq(pdev, 0);
1111 err = request_irq(dev->irq, ag71xx_interrupt,
1112 IRQF_DISABLED,
1113 dev->name, dev);
1114 if (err) {
1115 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1116 goto err_unmap_base;
1117 }
1118
1119 dev->base_addr = (unsigned long)ag->mac_base;
1120 dev->netdev_ops = &ag71xx_netdev_ops;
1121 dev->ethtool_ops = &ag71xx_ethtool_ops;
1122
1123 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1124
1125 init_timer(&ag->oom_timer);
1126 ag->oom_timer.data = (unsigned long) dev;
1127 ag->oom_timer.function = ag71xx_oom_timer_handler;
1128
1129 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1130 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1131
1132 ag->stop_desc = dma_alloc_coherent(NULL,
1133 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1134
1135 if (!ag->stop_desc)
1136 goto err_free_irq;
1137
1138 ag->stop_desc->data = 0;
1139 ag->stop_desc->ctrl = 0;
1140 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1141
1142 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1143
1144 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1145
1146 err = register_netdev(dev);
1147 if (err) {
1148 dev_err(&pdev->dev, "unable to register net device\n");
1149 goto err_free_desc;
1150 }
1151
1152 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1153 dev->name, dev->base_addr, dev->irq);
1154
1155 ag71xx_dump_regs(ag);
1156
1157 ag71xx_hw_init(ag);
1158
1159 ag71xx_dump_regs(ag);
1160
1161 err = ag71xx_phy_connect(ag);
1162 if (err)
1163 goto err_unregister_netdev;
1164
1165 err = ag71xx_debugfs_init(ag);
1166 if (err)
1167 goto err_phy_disconnect;
1168
1169 platform_set_drvdata(pdev, dev);
1170
1171 return 0;
1172
1173 err_phy_disconnect:
1174 ag71xx_phy_disconnect(ag);
1175 err_unregister_netdev:
1176 unregister_netdev(dev);
1177 err_free_desc:
1178 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1179 ag->stop_desc_dma);
1180 err_free_irq:
1181 free_irq(dev->irq, dev);
1182 err_unmap_base:
1183 iounmap(ag->mac_base);
1184 err_free_dev:
1185 kfree(dev);
1186 err_out:
1187 platform_set_drvdata(pdev, NULL);
1188 return err;
1189 }
1190
1191 static int __devexit ag71xx_remove(struct platform_device *pdev)
1192 {
1193 struct net_device *dev = platform_get_drvdata(pdev);
1194
1195 if (dev) {
1196 struct ag71xx *ag = netdev_priv(dev);
1197
1198 ag71xx_debugfs_exit(ag);
1199 ag71xx_phy_disconnect(ag);
1200 unregister_netdev(dev);
1201 free_irq(dev->irq, dev);
1202 iounmap(ag->mac_base);
1203 kfree(dev);
1204 platform_set_drvdata(pdev, NULL);
1205 }
1206
1207 return 0;
1208 }
1209
1210 static struct platform_driver ag71xx_driver = {
1211 .probe = ag71xx_probe,
1212 .remove = __exit_p(ag71xx_remove),
1213 .driver = {
1214 .name = AG71XX_DRV_NAME,
1215 }
1216 };
1217
1218 static int __init ag71xx_module_init(void)
1219 {
1220 int ret;
1221
1222 ret = ag71xx_debugfs_root_init();
1223 if (ret)
1224 goto err_out;
1225
1226 ret = ag71xx_mdio_driver_init();
1227 if (ret)
1228 goto err_debugfs_exit;
1229
1230 ret = platform_driver_register(&ag71xx_driver);
1231 if (ret)
1232 goto err_mdio_exit;
1233
1234 return 0;
1235
1236 err_mdio_exit:
1237 ag71xx_mdio_driver_exit();
1238 err_debugfs_exit:
1239 ag71xx_debugfs_root_exit();
1240 err_out:
1241 return ret;
1242 }
1243
1244 static void __exit ag71xx_module_exit(void)
1245 {
1246 platform_driver_unregister(&ag71xx_driver);
1247 ag71xx_mdio_driver_exit();
1248 ag71xx_debugfs_root_exit();
1249 }
1250
1251 module_init(ag71xx_module_init);
1252 module_exit(ag71xx_module_exit);
1253
1254 MODULE_VERSION(AG71XX_DRV_VERSION);
1255 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1256 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1257 MODULE_LICENSE("GPL v2");
1258 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt SVN history