ar71xx: add AR934x specific UART clock initialization
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ar71xx / devices.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22
23 #include <asm/mach-ar71xx/ar71xx.h>
24
25 #include "devices.h"
26
27 unsigned char ar71xx_mac_base[ETH_ALEN] __initdata;
28
29 static struct resource ar71xx_uart_resources[] = {
30 {
31 .start = AR71XX_UART_BASE,
32 .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
33 .flags = IORESOURCE_MEM,
34 },
35 };
36
37 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
38 static struct plat_serial8250_port ar71xx_uart_data[] = {
39 {
40 .mapbase = AR71XX_UART_BASE,
41 .irq = AR71XX_MISC_IRQ_UART,
42 .flags = AR71XX_UART_FLAGS,
43 .iotype = UPIO_MEM32,
44 .regshift = 2,
45 }, {
46 /* terminating entry */
47 }
48 };
49
50 static struct platform_device ar71xx_uart_device = {
51 .name = "serial8250",
52 .id = PLAT8250_DEV_PLATFORM,
53 .resource = ar71xx_uart_resources,
54 .num_resources = ARRAY_SIZE(ar71xx_uart_resources),
55 .dev = {
56 .platform_data = ar71xx_uart_data
57 },
58 };
59
60 void __init ar71xx_add_device_uart(void)
61 {
62 switch (ar71xx_soc) {
63 case AR71XX_SOC_AR7130:
64 case AR71XX_SOC_AR7141:
65 case AR71XX_SOC_AR7161:
66 case AR71XX_SOC_AR7240:
67 case AR71XX_SOC_AR7241:
68 case AR71XX_SOC_AR7242:
69 case AR71XX_SOC_AR9130:
70 case AR71XX_SOC_AR9132:
71 ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
72 break;
73
74 case AR71XX_SOC_AR9341:
75 case AR71XX_SOC_AR9342:
76 case AR71XX_SOC_AR9344:
77 ar71xx_uart_data[0].uartclk = ar934x_ref_freq;
78 break;
79
80 default:
81 BUG();
82
83 }
84 platform_device_register(&ar71xx_uart_device);
85 }
86
87 static struct resource ar71xx_mdio_resources[] = {
88 {
89 .name = "mdio_base",
90 .flags = IORESOURCE_MEM,
91 .start = AR71XX_GE0_BASE,
92 .end = AR71XX_GE0_BASE + 0x200 - 1,
93 }
94 };
95
96 static struct ag71xx_mdio_platform_data ar71xx_mdio_data;
97
98 struct platform_device ar71xx_mdio_device = {
99 .name = "ag71xx-mdio",
100 .id = -1,
101 .resource = ar71xx_mdio_resources,
102 .num_resources = ARRAY_SIZE(ar71xx_mdio_resources),
103 .dev = {
104 .platform_data = &ar71xx_mdio_data,
105 },
106 };
107
108 void __init ar71xx_add_device_mdio(u32 phy_mask)
109 {
110 switch (ar71xx_soc) {
111 case AR71XX_SOC_AR7240:
112 ar71xx_mdio_data.is_ar7240 = 1;
113 break;
114 case AR71XX_SOC_AR7241:
115 ar71xx_mdio_data.is_ar7240 = 1;
116 ar71xx_mdio_resources[0].start = AR71XX_GE1_BASE;
117 ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1;
118 break;
119 case AR71XX_SOC_AR7242:
120 ar71xx_mdio_data.is_ar7240 = 1;
121 break;
122 default:
123 break;
124 }
125
126 ar71xx_mdio_data.phy_mask = phy_mask;
127
128 platform_device_register(&ar71xx_mdio_device);
129 }
130
131 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
132 {
133 void __iomem *base;
134 u32 t;
135
136 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
137
138 t = __raw_readl(base + cfg_reg);
139 t &= ~(3 << shift);
140 t |= (2 << shift);
141 __raw_writel(t, base + cfg_reg);
142 udelay(100);
143
144 __raw_writel(pll_val, base + pll_reg);
145
146 t |= (3 << shift);
147 __raw_writel(t, base + cfg_reg);
148 udelay(100);
149
150 t &= ~(3 << shift);
151 __raw_writel(t, base + cfg_reg);
152 udelay(100);
153
154 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
155 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
156
157 iounmap(base);
158 }
159
160 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
161 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
162
163 static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
164 {
165 struct ar71xx_eth_pll_data *pll_data;
166 u32 pll_val;
167
168 switch (mac) {
169 case 0:
170 pll_data = &ar71xx_eth0_pll_data;
171 break;
172 case 1:
173 pll_data = &ar71xx_eth1_pll_data;
174 break;
175 default:
176 BUG();
177 }
178
179 switch (speed) {
180 case SPEED_10:
181 pll_val = pll_data->pll_10;
182 break;
183 case SPEED_100:
184 pll_val = pll_data->pll_100;
185 break;
186 case SPEED_1000:
187 pll_val = pll_data->pll_1000;
188 break;
189 default:
190 BUG();
191 }
192
193 return pll_val;
194 }
195
196 static void ar71xx_set_pll_ge0(int speed)
197 {
198 u32 val = ar71xx_get_eth_pll(0, speed);
199
200 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
201 val, AR71XX_ETH0_PLL_SHIFT);
202 }
203
204 static void ar71xx_set_pll_ge1(int speed)
205 {
206 u32 val = ar71xx_get_eth_pll(1, speed);
207
208 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
209 val, AR71XX_ETH1_PLL_SHIFT);
210 }
211
212 static void ar724x_set_pll_ge0(int speed)
213 {
214 /* TODO */
215 }
216
217 static void ar724x_set_pll_ge1(int speed)
218 {
219 /* TODO */
220 }
221
222 static void ar91xx_set_pll_ge0(int speed)
223 {
224 u32 val = ar71xx_get_eth_pll(0, speed);
225
226 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
227 val, AR91XX_ETH0_PLL_SHIFT);
228 }
229
230 static void ar91xx_set_pll_ge1(int speed)
231 {
232 u32 val = ar71xx_get_eth_pll(1, speed);
233
234 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
235 val, AR91XX_ETH1_PLL_SHIFT);
236 }
237
238 static void ar71xx_ddr_flush_ge0(void)
239 {
240 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
241 }
242
243 static void ar71xx_ddr_flush_ge1(void)
244 {
245 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
246 }
247
248 static void ar724x_ddr_flush_ge0(void)
249 {
250 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
251 }
252
253 static void ar724x_ddr_flush_ge1(void)
254 {
255 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
256 }
257
258 static void ar91xx_ddr_flush_ge0(void)
259 {
260 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
261 }
262
263 static void ar91xx_ddr_flush_ge1(void)
264 {
265 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
266 }
267
268 static struct resource ar71xx_eth0_resources[] = {
269 {
270 .name = "mac_base",
271 .flags = IORESOURCE_MEM,
272 .start = AR71XX_GE0_BASE,
273 .end = AR71XX_GE0_BASE + 0x200 - 1,
274 }, {
275 .name = "mii_ctrl",
276 .flags = IORESOURCE_MEM,
277 .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL,
278 .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
279 }, {
280 .name = "mac_irq",
281 .flags = IORESOURCE_IRQ,
282 .start = AR71XX_CPU_IRQ_GE0,
283 .end = AR71XX_CPU_IRQ_GE0,
284 },
285 };
286
287 struct ag71xx_platform_data ar71xx_eth0_data = {
288 .reset_bit = RESET_MODULE_GE0_MAC,
289 };
290
291 struct platform_device ar71xx_eth0_device = {
292 .name = "ag71xx",
293 .id = 0,
294 .resource = ar71xx_eth0_resources,
295 .num_resources = ARRAY_SIZE(ar71xx_eth0_resources),
296 .dev = {
297 .platform_data = &ar71xx_eth0_data,
298 },
299 };
300
301 static struct resource ar71xx_eth1_resources[] = {
302 {
303 .name = "mac_base",
304 .flags = IORESOURCE_MEM,
305 .start = AR71XX_GE1_BASE,
306 .end = AR71XX_GE1_BASE + 0x200 - 1,
307 }, {
308 .name = "mii_ctrl",
309 .flags = IORESOURCE_MEM,
310 .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL,
311 .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
312 }, {
313 .name = "mac_irq",
314 .flags = IORESOURCE_IRQ,
315 .start = AR71XX_CPU_IRQ_GE1,
316 .end = AR71XX_CPU_IRQ_GE1,
317 },
318 };
319
320 struct ag71xx_platform_data ar71xx_eth1_data = {
321 .reset_bit = RESET_MODULE_GE1_MAC,
322 };
323
324 struct platform_device ar71xx_eth1_device = {
325 .name = "ag71xx",
326 .id = 1,
327 .resource = ar71xx_eth1_resources,
328 .num_resources = ARRAY_SIZE(ar71xx_eth1_resources),
329 .dev = {
330 .platform_data = &ar71xx_eth1_data,
331 },
332 };
333
334 #define AR71XX_PLL_VAL_1000 0x00110000
335 #define AR71XX_PLL_VAL_100 0x00001099
336 #define AR71XX_PLL_VAL_10 0x00991099
337
338 #define AR724X_PLL_VAL_1000 0x00110000
339 #define AR724X_PLL_VAL_100 0x00001099
340 #define AR724X_PLL_VAL_10 0x00991099
341
342 #define AR91XX_PLL_VAL_1000 0x1a000000
343 #define AR91XX_PLL_VAL_100 0x13000a44
344 #define AR91XX_PLL_VAL_10 0x00441099
345
346 static void __init ar71xx_init_eth_pll_data(unsigned int id)
347 {
348 struct ar71xx_eth_pll_data *pll_data;
349 u32 pll_10, pll_100, pll_1000;
350
351 switch (id) {
352 case 0:
353 pll_data = &ar71xx_eth0_pll_data;
354 break;
355 case 1:
356 pll_data = &ar71xx_eth1_pll_data;
357 break;
358 default:
359 BUG();
360 }
361
362 switch (ar71xx_soc) {
363 case AR71XX_SOC_AR7130:
364 case AR71XX_SOC_AR7141:
365 case AR71XX_SOC_AR7161:
366 pll_10 = AR71XX_PLL_VAL_10;
367 pll_100 = AR71XX_PLL_VAL_100;
368 pll_1000 = AR71XX_PLL_VAL_1000;
369 break;
370
371 case AR71XX_SOC_AR7240:
372 case AR71XX_SOC_AR7241:
373 case AR71XX_SOC_AR7242:
374 pll_10 = AR724X_PLL_VAL_10;
375 pll_100 = AR724X_PLL_VAL_100;
376 pll_1000 = AR724X_PLL_VAL_1000;
377 break;
378
379 case AR71XX_SOC_AR9130:
380 case AR71XX_SOC_AR9132:
381 pll_10 = AR91XX_PLL_VAL_10;
382 pll_100 = AR91XX_PLL_VAL_100;
383 pll_1000 = AR91XX_PLL_VAL_1000;
384 break;
385 default:
386 BUG();
387 }
388
389 if (!pll_data->pll_10)
390 pll_data->pll_10 = pll_10;
391
392 if (!pll_data->pll_100)
393 pll_data->pll_100 = pll_100;
394
395 if (!pll_data->pll_1000)
396 pll_data->pll_1000 = pll_1000;
397 }
398
399 static int ar71xx_eth_instance __initdata;
400 void __init ar71xx_add_device_eth(unsigned int id)
401 {
402 struct platform_device *pdev;
403 struct ag71xx_platform_data *pdata;
404
405 ar71xx_init_eth_pll_data(id);
406
407 switch (id) {
408 case 0:
409 switch (ar71xx_eth0_data.phy_if_mode) {
410 case PHY_INTERFACE_MODE_MII:
411 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII;
412 break;
413 case PHY_INTERFACE_MODE_GMII:
414 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII;
415 break;
416 case PHY_INTERFACE_MODE_RGMII:
417 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII;
418 break;
419 case PHY_INTERFACE_MODE_RMII:
420 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII;
421 break;
422 default:
423 printk(KERN_ERR "ar71xx: invalid PHY interface mode "
424 "for eth0\n");
425 return;
426 }
427 pdev = &ar71xx_eth0_device;
428 break;
429 case 1:
430 switch (ar71xx_eth1_data.phy_if_mode) {
431 case PHY_INTERFACE_MODE_RMII:
432 ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII;
433 break;
434 case PHY_INTERFACE_MODE_RGMII:
435 ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII;
436 break;
437 default:
438 printk(KERN_ERR "ar71xx: invalid PHY interface mode "
439 "for eth1\n");
440 return;
441 }
442 pdev = &ar71xx_eth1_device;
443 break;
444 default:
445 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
446 return;
447 }
448
449 pdata = pdev->dev.platform_data;
450
451 switch (ar71xx_soc) {
452 case AR71XX_SOC_AR7130:
453 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
454 : ar71xx_ddr_flush_ge0;
455 pdata->set_pll = id ? ar71xx_set_pll_ge1
456 : ar71xx_set_pll_ge0;
457 break;
458
459 case AR71XX_SOC_AR7141:
460 case AR71XX_SOC_AR7161:
461 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
462 : ar71xx_ddr_flush_ge0;
463 pdata->set_pll = id ? ar71xx_set_pll_ge1
464 : ar71xx_set_pll_ge0;
465 pdata->has_gbit = 1;
466 break;
467
468 case AR71XX_SOC_AR7241:
469 case AR71XX_SOC_AR7242:
470 ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
471 ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
472 /* fall through */
473 case AR71XX_SOC_AR7240:
474 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
475 : ar724x_ddr_flush_ge0;
476 pdata->set_pll = id ? ar724x_set_pll_ge1
477 : ar724x_set_pll_ge0;
478 pdata->is_ar724x = 1;
479
480 if (!pdata->fifo_cfg1)
481 pdata->fifo_cfg1 = 0x0010ffff;
482 if (!pdata->fifo_cfg2)
483 pdata->fifo_cfg2 = 0x015500aa;
484 if (!pdata->fifo_cfg3)
485 pdata->fifo_cfg3 = 0x01f00140;
486 break;
487
488 case AR71XX_SOC_AR9130:
489 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
490 : ar91xx_ddr_flush_ge0;
491 pdata->set_pll = id ? ar91xx_set_pll_ge1
492 : ar91xx_set_pll_ge0;
493 pdata->is_ar91xx = 1;
494 break;
495
496 case AR71XX_SOC_AR9132:
497 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
498 : ar91xx_ddr_flush_ge0;
499 pdata->set_pll = id ? ar91xx_set_pll_ge1
500 : ar91xx_set_pll_ge0;
501 pdata->is_ar91xx = 1;
502 pdata->has_gbit = 1;
503 break;
504
505 default:
506 BUG();
507 }
508
509 switch (pdata->phy_if_mode) {
510 case PHY_INTERFACE_MODE_GMII:
511 case PHY_INTERFACE_MODE_RGMII:
512 if (!pdata->has_gbit) {
513 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
514 id);
515 return;
516 }
517 /* fallthrough */
518 default:
519 break;
520 }
521
522 if (!is_valid_ether_addr(pdata->mac_addr)) {
523 random_ether_addr(pdata->mac_addr);
524 printk(KERN_DEBUG
525 "ar71xx: using random MAC address for eth%d\n",
526 ar71xx_eth_instance);
527 }
528
529 if (pdata->mii_bus_dev == NULL)
530 pdata->mii_bus_dev = &ar71xx_mdio_device.dev;
531
532 /* Reset the device */
533 ar71xx_device_stop(pdata->reset_bit);
534 mdelay(100);
535
536 ar71xx_device_start(pdata->reset_bit);
537 mdelay(100);
538
539 platform_device_register(pdev);
540 ar71xx_eth_instance++;
541 }
542
543 static struct resource ar71xx_spi_resources[] = {
544 [0] = {
545 .start = AR71XX_SPI_BASE,
546 .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
547 .flags = IORESOURCE_MEM,
548 },
549 };
550
551 static struct platform_device ar71xx_spi_device = {
552 .name = "ar71xx-spi",
553 .id = -1,
554 .resource = ar71xx_spi_resources,
555 .num_resources = ARRAY_SIZE(ar71xx_spi_resources),
556 };
557
558 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
559 struct spi_board_info const *info,
560 unsigned n)
561 {
562 spi_register_board_info(info, n);
563 ar71xx_spi_device.dev.platform_data = pdata;
564 platform_device_register(&ar71xx_spi_device);
565 }
566
567 void __init ar71xx_add_device_wdt(void)
568 {
569 platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
570 }
571
572 void __init ar71xx_set_mac_base(unsigned char *mac)
573 {
574 memcpy(ar71xx_mac_base, mac, ETH_ALEN);
575 }
576
577 void __init ar71xx_parse_mac_addr(char *mac_str)
578 {
579 u8 tmp[ETH_ALEN];
580 int t;
581
582 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
583 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
584
585 if (t != ETH_ALEN)
586 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
587 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
588
589 if (t == ETH_ALEN)
590 ar71xx_set_mac_base(tmp);
591 else
592 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
593 "\"%s\"\n", mac_str);
594 }
595
596 static int __init ar71xx_ethaddr_setup(char *str)
597 {
598 ar71xx_parse_mac_addr(str);
599 return 1;
600 }
601 __setup("ethaddr=", ar71xx_ethaddr_setup);
602
603 static int __init ar71xx_kmac_setup(char *str)
604 {
605 ar71xx_parse_mac_addr(str);
606 return 1;
607 }
608 __setup("kmac=", ar71xx_kmac_setup);
609
610 void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
611 unsigned offset)
612 {
613 u32 t;
614
615 if (!is_valid_ether_addr(src)) {
616 memset(dst, '\0', ETH_ALEN);
617 return;
618 }
619
620 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
621 t += offset;
622
623 dst[0] = src[0];
624 dst[1] = src[1];
625 dst[2] = src[2];
626 dst[3] = (t >> 16) & 0xff;
627 dst[4] = (t >> 8) & 0xff;
628 dst[5] = t & 0xff;
629 }