[ar71xx] build images for the AP83 board
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ar71xx / irq.c
1 /*
2 * Atheros AR71xx SoC specific interrupt handling
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
21
22 #include <asm/mach-ar71xx/ar71xx.h>
23
24 #ifdef CONFIG_PCI
25 static void ar71xx_pci_irq_dispatch(void)
26 {
27 u32 pending;
28
29 pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
30 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
31
32 if (pending & PCI_INT_DEV0)
33 do_IRQ(AR71XX_PCI_IRQ_DEV0);
34
35 else if (pending & PCI_INT_DEV1)
36 do_IRQ(AR71XX_PCI_IRQ_DEV1);
37
38 else if (pending & PCI_INT_DEV2)
39 do_IRQ(AR71XX_PCI_IRQ_DEV2);
40
41 else
42 spurious_interrupt();
43 }
44
45 static void ar71xx_pci_irq_unmask(unsigned int irq)
46 {
47 irq -= AR71XX_PCI_IRQ_BASE;
48 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
49 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
50 }
51
52 static void ar71xx_pci_irq_mask(unsigned int irq)
53 {
54 irq -= AR71XX_PCI_IRQ_BASE;
55 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
56 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
57 }
58
59 static struct irq_chip ar71xx_pci_irq_chip = {
60 .name = "AR71XX PCI ",
61 .mask = ar71xx_pci_irq_mask,
62 .unmask = ar71xx_pci_irq_unmask,
63 .mask_ack = ar71xx_pci_irq_mask,
64 };
65
66 static struct irqaction ar71xx_pci_irqaction = {
67 .handler = no_action,
68 .name = "cascade [AR71XX PCI]",
69 };
70
71 static void __init ar71xx_pci_irq_init(void)
72 {
73 int i;
74
75 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
76 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
77
78 for (i = AR71XX_PCI_IRQ_BASE;
79 i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
80 irq_desc[i].status = IRQ_DISABLED;
81 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
82 handle_level_irq);
83 }
84
85 setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
86 }
87 #endif /* CONFIG_PCI */
88
89 static void ar71xx_gpio_irq_dispatch(void)
90 {
91 u32 pending;
92
93 pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
94 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
95
96 if (pending)
97 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
98 else
99 spurious_interrupt();
100 }
101
102 static void ar71xx_gpio_irq_unmask(unsigned int irq)
103 {
104 irq -= AR71XX_GPIO_IRQ_BASE;
105 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
106 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
107 }
108
109 static void ar71xx_gpio_irq_mask(unsigned int irq)
110 {
111 irq -= AR71XX_GPIO_IRQ_BASE;
112 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
113 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
114 }
115
116 #if 0
117 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
118 {
119 /* TODO: implement */
120 return 0;
121 }
122 #else
123 #define ar71xx_gpio_irq_set_type NULL
124 #endif
125
126 struct irq_chip ar71xx_gpio_irq_chip = {
127 .name = "AR71XX GPIO",
128 .unmask = ar71xx_gpio_irq_unmask,
129 .mask = ar71xx_gpio_irq_mask,
130 .mask_ack = ar71xx_gpio_irq_mask,
131 .set_type = ar71xx_gpio_irq_set_type,
132 };
133
134 static struct irqaction ar71xx_gpio_irqaction = {
135 .handler = no_action,
136 .name = "cascade [AR71XX GPIO]",
137 };
138
139 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
140 #define GPIO_INT_ALL 0xffff
141
142 static void __init ar71xx_gpio_irq_init(void)
143 {
144 int i;
145
146 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
147 ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
148
149 /* setup type of all GPIO interrupts to level sensitive */
150 ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
151
152 /* setup polarity of all GPIO interrupts to active high */
153 ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
154
155 for (i = AR71XX_GPIO_IRQ_BASE;
156 i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
157 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
158 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
159 handle_level_irq);
160 }
161
162 setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
163 }
164
165 static void ar71xx_misc_irq_dispatch(void)
166 {
167 u32 pending;
168
169 pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
170 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
171
172 if (pending & MISC_INT_UART)
173 do_IRQ(AR71XX_MISC_IRQ_UART);
174
175 else if (pending & MISC_INT_DMA)
176 do_IRQ(AR71XX_MISC_IRQ_DMA);
177
178 else if (pending & MISC_INT_PERFC)
179 do_IRQ(AR71XX_MISC_IRQ_PERFC);
180
181 else if (pending & MISC_INT_TIMER)
182 do_IRQ(AR71XX_MISC_IRQ_TIMER);
183
184 else if (pending & MISC_INT_OHCI)
185 do_IRQ(AR71XX_MISC_IRQ_OHCI);
186
187 else if (pending & MISC_INT_ERROR)
188 do_IRQ(AR71XX_MISC_IRQ_ERROR);
189
190 else if (pending & MISC_INT_GPIO)
191 ar71xx_gpio_irq_dispatch();
192
193 else if (pending & MISC_INT_WDOG)
194 do_IRQ(AR71XX_MISC_IRQ_WDOG);
195
196 else
197 spurious_interrupt();
198 }
199
200 static void ar71xx_misc_irq_unmask(unsigned int irq)
201 {
202 irq -= AR71XX_MISC_IRQ_BASE;
203 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
204 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
205 }
206
207 static void ar71xx_misc_irq_mask(unsigned int irq)
208 {
209 irq -= AR71XX_MISC_IRQ_BASE;
210 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
211 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
212 }
213
214 struct irq_chip ar71xx_misc_irq_chip = {
215 .name = "AR71XX MISC",
216 .unmask = ar71xx_misc_irq_unmask,
217 .mask = ar71xx_misc_irq_mask,
218 .mask_ack = ar71xx_misc_irq_mask,
219 };
220
221 static struct irqaction ar71xx_misc_irqaction = {
222 .handler = no_action,
223 .name = "cascade [AR71XX MISC]",
224 };
225
226 static void __init ar71xx_misc_irq_init(void)
227 {
228 int i;
229
230 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
231 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
232
233 for (i = AR71XX_MISC_IRQ_BASE;
234 i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
235 irq_desc[i].status = IRQ_DISABLED;
236 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
237 handle_level_irq);
238 }
239
240 setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
241 }
242
243 static void ar913x_wmac_irq_dispatch(void)
244 {
245 do_IRQ(AR71XX_CPU_IRQ_WMAC);
246 }
247
248 static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
249
250 asmlinkage void plat_irq_dispatch(void)
251 {
252 unsigned long pending;
253
254 pending = read_c0_status() & read_c0_cause() & ST0_IM;
255
256 if (pending & STATUSF_IP7)
257 do_IRQ(AR71XX_CPU_IRQ_TIMER);
258
259 else if (pending & STATUSF_IP2)
260 ar71xx_ip2_irq_handler();
261
262 else if (pending & STATUSF_IP4)
263 do_IRQ(AR71XX_CPU_IRQ_GE0);
264
265 else if (pending & STATUSF_IP5)
266 do_IRQ(AR71XX_CPU_IRQ_GE1);
267
268 else if (pending & STATUSF_IP3)
269 do_IRQ(AR71XX_CPU_IRQ_USB);
270
271 else if (pending & STATUSF_IP6)
272 ar71xx_misc_irq_dispatch();
273
274 else
275 spurious_interrupt();
276 }
277
278 void __init arch_init_irq(void)
279 {
280 mips_cpu_irq_init();
281
282 ar71xx_misc_irq_init();
283
284 switch (ar71xx_soc) {
285 case AR71XX_SOC_AR7130:
286 case AR71XX_SOC_AR7141:
287 case AR71XX_SOC_AR7161:
288 #ifdef CONFIG_PCI
289 ar71xx_pci_irq_init();
290 ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
291 #endif
292 break;
293 case AR71XX_SOC_AR9130:
294 case AR71XX_SOC_AR9132:
295 ar71xx_ip2_irq_handler = ar913x_wmac_irq_dispatch;
296 break;
297 default:
298 BUG();
299 }
300
301 ar71xx_gpio_irq_init();
302 }