ar71xx: add AR934x specific glue for IRQ initialization
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ar71xx / irq.c
1 /*
2 * Atheros AR71xx SoC specific interrupt handling
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20
21 #include <asm/irq_cpu.h>
22 #include <asm/mipsregs.h>
23
24 #include <asm/mach-ar71xx/ar71xx.h>
25
26 static int ip2_flush_reg;
27
28 static void ar71xx_gpio_irq_dispatch(void)
29 {
30 void __iomem *base = ar71xx_gpio_base;
31 u32 pending;
32
33 pending = __raw_readl(base + GPIO_REG_INT_PENDING) &
34 __raw_readl(base + GPIO_REG_INT_ENABLE);
35
36 if (pending)
37 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
38 else
39 spurious_interrupt();
40 }
41
42 static void ar71xx_gpio_irq_unmask(unsigned int irq)
43 {
44 void __iomem *base = ar71xx_gpio_base;
45 u32 t;
46
47 irq -= AR71XX_GPIO_IRQ_BASE;
48
49 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
50 __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE);
51
52 /* flush write */
53 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
54 }
55
56 static void ar71xx_gpio_irq_mask(unsigned int irq)
57 {
58 void __iomem *base = ar71xx_gpio_base;
59 u32 t;
60
61 irq -= AR71XX_GPIO_IRQ_BASE;
62
63 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
64 __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE);
65
66 /* flush write */
67 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
68 }
69
70 #if 0
71 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
72 {
73 /* TODO: implement */
74 return 0;
75 }
76 #else
77 #define ar71xx_gpio_irq_set_type NULL
78 #endif
79
80 static struct irq_chip ar71xx_gpio_irq_chip = {
81 .name = "AR71XX GPIO",
82 .unmask = ar71xx_gpio_irq_unmask,
83 .mask = ar71xx_gpio_irq_mask,
84 .mask_ack = ar71xx_gpio_irq_mask,
85 .set_type = ar71xx_gpio_irq_set_type,
86 };
87
88 static struct irqaction ar71xx_gpio_irqaction = {
89 .handler = no_action,
90 .name = "cascade [AR71XX GPIO]",
91 };
92
93 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
94 #define GPIO_INT_ALL 0xffff
95
96 static void __init ar71xx_gpio_irq_init(void)
97 {
98 void __iomem *base = ar71xx_gpio_base;
99 int i;
100
101 __raw_writel(0, base + GPIO_REG_INT_ENABLE);
102 __raw_writel(0, base + GPIO_REG_INT_PENDING);
103
104 /* setup type of all GPIO interrupts to level sensitive */
105 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE);
106
107 /* setup polarity of all GPIO interrupts to active high */
108 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY);
109
110 for (i = AR71XX_GPIO_IRQ_BASE;
111 i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
112 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
113 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
114 handle_level_irq);
115 }
116
117 setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
118 }
119
120 static void ar71xx_misc_irq_dispatch(void)
121 {
122 u32 pending;
123
124 pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
125 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
126
127 if (pending & MISC_INT_UART)
128 do_IRQ(AR71XX_MISC_IRQ_UART);
129
130 else if (pending & MISC_INT_DMA)
131 do_IRQ(AR71XX_MISC_IRQ_DMA);
132
133 else if (pending & MISC_INT_PERFC)
134 do_IRQ(AR71XX_MISC_IRQ_PERFC);
135
136 else if (pending & MISC_INT_TIMER)
137 do_IRQ(AR71XX_MISC_IRQ_TIMER);
138
139 else if (pending & MISC_INT_OHCI)
140 do_IRQ(AR71XX_MISC_IRQ_OHCI);
141
142 else if (pending & MISC_INT_ERROR)
143 do_IRQ(AR71XX_MISC_IRQ_ERROR);
144
145 else if (pending & MISC_INT_GPIO)
146 ar71xx_gpio_irq_dispatch();
147
148 else if (pending & MISC_INT_WDOG)
149 do_IRQ(AR71XX_MISC_IRQ_WDOG);
150
151 else if (pending & MISC_INT_TIMER2)
152 do_IRQ(AR71XX_MISC_IRQ_TIMER2);
153
154 else if (pending & MISC_INT_TIMER3)
155 do_IRQ(AR71XX_MISC_IRQ_TIMER3);
156
157 else if (pending & MISC_INT_TIMER4)
158 do_IRQ(AR71XX_MISC_IRQ_TIMER4);
159
160 else if (pending & MISC_INT_DDR_PERF)
161 do_IRQ(AR71XX_MISC_IRQ_DDR_PERF);
162
163 else if (pending & MISC_INT_ENET_LINK)
164 do_IRQ(AR71XX_MISC_IRQ_ENET_LINK);
165
166 else
167 spurious_interrupt();
168 }
169
170 static void ar71xx_misc_irq_unmask(unsigned int irq)
171 {
172 void __iomem *base = ar71xx_reset_base;
173 u32 t;
174
175 irq -= AR71XX_MISC_IRQ_BASE;
176
177 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
178 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
179
180 /* flush write */
181 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
182 }
183
184 static void ar71xx_misc_irq_mask(unsigned int irq)
185 {
186 void __iomem *base = ar71xx_reset_base;
187 u32 t;
188
189 irq -= AR71XX_MISC_IRQ_BASE;
190
191 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
192 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
193
194 /* flush write */
195 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
196 }
197
198 static void ar724x_misc_irq_ack(unsigned int irq)
199 {
200 void __iomem *base = ar71xx_reset_base;
201 u32 t;
202
203 irq -= AR71XX_MISC_IRQ_BASE;
204
205 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
206 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
207
208 /* flush write */
209 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
210 }
211
212 static struct irq_chip ar71xx_misc_irq_chip = {
213 .name = "AR71XX MISC",
214 .unmask = ar71xx_misc_irq_unmask,
215 .mask = ar71xx_misc_irq_mask,
216 };
217
218 static struct irqaction ar71xx_misc_irqaction = {
219 .handler = no_action,
220 .name = "cascade [AR71XX MISC]",
221 };
222
223 static void __init ar71xx_misc_irq_init(void)
224 {
225 void __iomem *base = ar71xx_reset_base;
226 int i;
227
228 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
229 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
230
231 switch (ar71xx_soc) {
232 case AR71XX_SOC_AR7240:
233 case AR71XX_SOC_AR7241:
234 case AR71XX_SOC_AR7242:
235 case AR71XX_SOC_AR9341:
236 case AR71XX_SOC_AR9342:
237 case AR71XX_SOC_AR9344:
238 ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
239 break;
240 default:
241 ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
242 break;
243 }
244
245 for (i = AR71XX_MISC_IRQ_BASE;
246 i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
247 irq_desc[i].status = IRQ_DISABLED;
248 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
249 handle_level_irq);
250 }
251
252 setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
253 }
254
255 asmlinkage void plat_irq_dispatch(void)
256 {
257 unsigned long pending;
258
259 pending = read_c0_status() & read_c0_cause() & ST0_IM;
260
261 if (pending & STATUSF_IP7)
262 do_IRQ(AR71XX_CPU_IRQ_TIMER);
263
264 else if (pending & STATUSF_IP2) {
265 /*
266 * This IRQ is meant for a PCI device. Drivers for PCI devices
267 * typically allocate coherent DMA memory for the descriptor
268 * ring, however the DMA controller may still have some
269 * unsynchronized data in the FIFO.
270 * Issue a flush here to ensure that the driver sees the update.
271 */
272 ar71xx_ddr_flush(ip2_flush_reg);
273 do_IRQ(AR71XX_CPU_IRQ_IP2);
274 }
275
276 else if (pending & STATUSF_IP4)
277 do_IRQ(AR71XX_CPU_IRQ_GE0);
278
279 else if (pending & STATUSF_IP5)
280 do_IRQ(AR71XX_CPU_IRQ_GE1);
281
282 else if (pending & STATUSF_IP3)
283 do_IRQ(AR71XX_CPU_IRQ_USB);
284
285 else if (pending & STATUSF_IP6)
286 ar71xx_misc_irq_dispatch();
287
288 else
289 spurious_interrupt();
290 }
291
292 void __init arch_init_irq(void)
293 {
294 switch (ar71xx_soc) {
295 case AR71XX_SOC_AR7240:
296 case AR71XX_SOC_AR7241:
297 case AR71XX_SOC_AR7242:
298 ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
299 break;
300 case AR71XX_SOC_AR9130:
301 case AR71XX_SOC_AR9132:
302 ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC;
303 break;
304 case AR71XX_SOC_AR9341:
305 case AR71XX_SOC_AR9342:
306 case AR71XX_SOC_AR9344:
307 ip2_flush_reg = AR934X_DDR_REG_FLUSH_PCIE;
308 break;
309
310 default:
311 ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
312 break;
313 }
314
315 mips_cpu_irq_init();
316
317 ar71xx_misc_irq_init();
318
319 cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
320
321 ar71xx_gpio_irq_init();
322 }