target/linux/ar71xx/files/arch/mips/ar71xx/irq.c

   1 /*
   2  *  Atheros AR71xx SoC specific interrupt handling
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18
  19 #include <asm/irq_cpu.h>
  20 #include <asm/mipsregs.h>
  21
  22 #include <asm/mach-ar71xx/ar71xx.h>
  23
  24 #ifdef CONFIG_PCI
  25 static void ar71xx_pci_irq_dispatch(void)
  26 {
  27         u32 pending;
  28
  29         pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
  30                   ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  31
  32         if (pending & PCI_INT_DEV0)
  33                 do_IRQ(AR71XX_PCI_IRQ_DEV0);
  34
  35         else if (pending & PCI_INT_DEV1)
  36                 do_IRQ(AR71XX_PCI_IRQ_DEV1);
  37
  38         else if (pending & PCI_INT_DEV2)
  39                 do_IRQ(AR71XX_PCI_IRQ_DEV2);
  40
  41         else if (pending & PCI_INT_CORE)
  42                 do_IRQ(AR71XX_PCI_IRQ_CORE);
  43
  44         else
  45                 spurious_interrupt();
  46 }
  47
  48 static void ar71xx_pci_irq_unmask(unsigned int irq)
  49 {
  50         irq -= AR71XX_PCI_IRQ_BASE;
  51         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
  52                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
  53
  54         /* flush write */
  55         ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  56 }
  57
  58 static void ar71xx_pci_irq_mask(unsigned int irq)
  59 {
  60         irq -= AR71XX_PCI_IRQ_BASE;
  61         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
  62                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
  63
  64         /* flush write */
  65         ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  66 }
  67
  68 static struct irq_chip ar71xx_pci_irq_chip = {
  69         .name           = "AR71XX PCI ",
  70         .mask           = ar71xx_pci_irq_mask,
  71         .unmask         = ar71xx_pci_irq_unmask,
  72         .mask_ack       = ar71xx_pci_irq_mask,
  73 };
  74
  75 static struct irqaction ar71xx_pci_irqaction = {
  76         .handler        = no_action,
  77         .name           = "cascade [AR71XX PCI]",
  78 };
  79
  80 static void __init ar71xx_pci_irq_init(void)
  81 {
  82         int i;
  83
  84         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
  85         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
  86
  87         for (i = AR71XX_PCI_IRQ_BASE;
  88              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
  89                 irq_desc[i].status = IRQ_DISABLED;
  90                 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
  91                                          handle_level_irq);
  92         }
  93
  94         setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
  95 }
  96
  97 static void ar724x_pci_irq_dispatch(void)
  98 {
  99         u32 pending;
 100
 101         pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) &
 102                   ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 103
 104         if (pending & AR724X_PCI_INT_DEV0)
 105                 do_IRQ(AR71XX_PCI_IRQ_DEV0);
 106
 107         else
 108                 spurious_interrupt();
 109 }
 110
 111 static void ar724x_pci_irq_unmask(unsigned int irq)
 112 {
 113         switch (irq) {
 114         case AR71XX_PCI_IRQ_DEV0:
 115                 irq -= AR71XX_PCI_IRQ_BASE;
 116                 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
 117                               ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) |
 118                                             AR724X_PCI_INT_DEV0);
 119                 /* flush write */
 120                 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 121         }
 122 }
 123
 124 static void ar724x_pci_irq_mask(unsigned int irq)
 125 {
 126         switch (irq) {
 127         case AR71XX_PCI_IRQ_DEV0:
 128                 irq -= AR71XX_PCI_IRQ_BASE;
 129                 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
 130                               ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) &
 131                                             ~AR724X_PCI_INT_DEV0);
 132                 /* flush write */
 133                 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 134
 135                 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS,
 136                               ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) |
 137                                             AR724X_PCI_INT_DEV0);
 138                 /* flush write */
 139                 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS);
 140         }
 141 }
 142
 143 static struct irq_chip ar724x_pci_irq_chip = {
 144         .name           = "AR724X PCI ",
 145         .mask           = ar724x_pci_irq_mask,
 146         .unmask         = ar724x_pci_irq_unmask,
 147         .mask_ack       = ar724x_pci_irq_mask,
 148 };
 149
 150 static struct irqaction ar724x_pci_irqaction = {
 151         .handler        = no_action,
 152         .name           = "cascade [AR724X PCI]",
 153 };
 154
 155 static void __init ar724x_pci_irq_init(void)
 156 {
 157         int i;
 158
 159         ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
 160         ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
 161
 162         for (i = AR71XX_PCI_IRQ_BASE;
 163              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
 164                 irq_desc[i].status = IRQ_DISABLED;
 165                 set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
 166                                          handle_level_irq);
 167         }
 168
 169         setup_irq(AR71XX_CPU_IRQ_PCI, &ar724x_pci_irqaction);
 170 }
 171 #endif /* CONFIG_PCI */
 172
 173 static void ar71xx_gpio_irq_dispatch(void)
 174 {
 175         u32 pending;
 176
 177         pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
 178                 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 179
 180         if (pending)
 181                 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
 182         else
 183                 spurious_interrupt();
 184 }
 185
 186 static void ar71xx_gpio_irq_unmask(unsigned int irq)
 187 {
 188         irq -= AR71XX_GPIO_IRQ_BASE;
 189         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
 190                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
 191
 192         /* flush write */
 193         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 194 }
 195
 196 static void ar71xx_gpio_irq_mask(unsigned int irq)
 197 {
 198         irq -= AR71XX_GPIO_IRQ_BASE;
 199         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
 200                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
 201
 202         /* flush write */
 203         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 204 }
 205
 206 #if 0
 207 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
 208 {
 209         /* TODO: implement */
 210         return 0;
 211 }
 212 #else
 213 #define ar71xx_gpio_irq_set_type        NULL
 214 #endif
 215
 216 struct irq_chip ar71xx_gpio_irq_chip = {
 217         .name           = "AR71XX GPIO",
 218         .unmask         = ar71xx_gpio_irq_unmask,
 219         .mask           = ar71xx_gpio_irq_mask,
 220         .mask_ack       = ar71xx_gpio_irq_mask,
 221         .set_type       = ar71xx_gpio_irq_set_type,
 222 };
 223
 224 static struct irqaction ar71xx_gpio_irqaction = {
 225         .handler        = no_action,
 226         .name           = "cascade [AR71XX GPIO]",
 227 };
 228
 229 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
 230 #define GPIO_INT_ALL    0xffff
 231
 232 static void __init ar71xx_gpio_irq_init(void)
 233 {
 234         int i;
 235
 236         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
 237         ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
 238
 239         /* setup type of all GPIO interrupts to level sensitive */
 240         ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
 241
 242         /* setup polarity of all GPIO interrupts to active high */
 243         ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
 244
 245         for (i = AR71XX_GPIO_IRQ_BASE;
 246              i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
 247                 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
 248                 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
 249                                          handle_level_irq);
 250         }
 251
 252         setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
 253 }
 254
 255 static void ar71xx_misc_irq_dispatch(void)
 256 {
 257         u32 pending;
 258
 259         pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
 260             & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 261
 262         if (pending & MISC_INT_UART)
 263                 do_IRQ(AR71XX_MISC_IRQ_UART);
 264
 265         else if (pending & MISC_INT_DMA)
 266                 do_IRQ(AR71XX_MISC_IRQ_DMA);
 267
 268         else if (pending & MISC_INT_PERFC)
 269                 do_IRQ(AR71XX_MISC_IRQ_PERFC);
 270
 271         else if (pending & MISC_INT_TIMER)
 272                 do_IRQ(AR71XX_MISC_IRQ_TIMER);
 273
 274         else if (pending & MISC_INT_OHCI)
 275                 do_IRQ(AR71XX_MISC_IRQ_OHCI);
 276
 277         else if (pending & MISC_INT_ERROR)
 278                 do_IRQ(AR71XX_MISC_IRQ_ERROR);
 279
 280         else if (pending & MISC_INT_GPIO)
 281                 ar71xx_gpio_irq_dispatch();
 282
 283         else if (pending & MISC_INT_WDOG)
 284                 do_IRQ(AR71XX_MISC_IRQ_WDOG);
 285
 286         else
 287                 spurious_interrupt();
 288 }
 289
 290 static void ar71xx_misc_irq_unmask(unsigned int irq)
 291 {
 292         irq -= AR71XX_MISC_IRQ_BASE;
 293         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 294                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
 295
 296         /* flush write */
 297         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 298 }
 299
 300 static void ar71xx_misc_irq_mask(unsigned int irq)
 301 {
 302         irq -= AR71XX_MISC_IRQ_BASE;
 303         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 304                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
 305
 306         /* flush write */
 307         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 308 }
 309
 310 struct irq_chip ar71xx_misc_irq_chip = {
 311         .name           = "AR71XX MISC",
 312         .unmask         = ar71xx_misc_irq_unmask,
 313         .mask           = ar71xx_misc_irq_mask,
 314         .mask_ack       = ar71xx_misc_irq_mask,
 315 };
 316
 317 static struct irqaction ar71xx_misc_irqaction = {
 318         .handler        = no_action,
 319         .name           = "cascade [AR71XX MISC]",
 320 };
 321
 322 static void __init ar71xx_misc_irq_init(void)
 323 {
 324         int i;
 325
 326         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
 327         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
 328
 329         for (i = AR71XX_MISC_IRQ_BASE;
 330              i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
 331                 irq_desc[i].status = IRQ_DISABLED;
 332                 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
 333                                          handle_level_irq);
 334         }
 335
 336         setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
 337 }
 338
 339 static void ar913x_wmac_irq_dispatch(void)
 340 {
 341         do_IRQ(AR71XX_CPU_IRQ_WMAC);
 342 }
 343
 344 static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
 345
 346 asmlinkage void plat_irq_dispatch(void)
 347 {
 348         unsigned long pending;
 349
 350         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 351
 352         if (pending & STATUSF_IP7)
 353                 do_IRQ(AR71XX_CPU_IRQ_TIMER);
 354
 355         else if (pending & STATUSF_IP2)
 356                 ar71xx_ip2_irq_handler();
 357
 358         else if (pending & STATUSF_IP4)
 359                 do_IRQ(AR71XX_CPU_IRQ_GE0);
 360
 361         else if (pending & STATUSF_IP5)
 362                 do_IRQ(AR71XX_CPU_IRQ_GE1);
 363
 364         else if (pending & STATUSF_IP3)
 365                 do_IRQ(AR71XX_CPU_IRQ_USB);
 366
 367         else if (pending & STATUSF_IP6)
 368                 ar71xx_misc_irq_dispatch();
 369
 370         else
 371                 spurious_interrupt();
 372 }
 373
 374 void __init arch_init_irq(void)
 375 {
 376         mips_cpu_irq_init();
 377
 378         ar71xx_misc_irq_init();
 379
 380         switch (ar71xx_soc) {
 381         case AR71XX_SOC_AR7130:
 382         case AR71XX_SOC_AR7141:
 383         case AR71XX_SOC_AR7161:
 384 #ifdef CONFIG_PCI
 385                 ar71xx_pci_irq_init();
 386                 ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
 387 #endif
 388         case AR71XX_SOC_AR7240:
 389 #ifdef CONFIG_PCI
 390                 ar724x_pci_irq_init();
 391                 ar71xx_ip2_irq_handler = ar724x_pci_irq_dispatch;
 392 #endif
 393                 break;
 394         case AR71XX_SOC_AR9130:
 395         case AR71XX_SOC_AR9132:
 396                 ar71xx_ip2_irq_handler = ar913x_wmac_irq_dispatch;
 397                 break;
 398         default:
 399                 BUG();
 400         }
 401
 402         ar71xx_gpio_irq_init();
 403 }