target/linux/ar71xx/files/arch/mips/ar71xx/irq.c

   1 /*
   2  *  Atheros AR71xx SoC specific interrupt handling
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18
  19 #include <asm/irq_cpu.h>
  20 #include <asm/mipsregs.h>
  21
  22 #include <asm/mach-ar71xx/ar71xx.h>
  23
  24 #ifdef CONFIG_PCI
  25 static void ar71xx_pci_irq_dispatch(void)
  26 {
  27         u32 pending;
  28
  29         pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
  30             ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  31
  32         if (pending & PCI_INT_DEV0)
  33                 do_IRQ(AR71XX_PCI_IRQ_DEV0);
  34
  35         else if (pending & PCI_INT_DEV1)
  36                 do_IRQ(AR71XX_PCI_IRQ_DEV1);
  37
  38         else if (pending & PCI_INT_DEV2)
  39                 do_IRQ(AR71XX_PCI_IRQ_DEV2);
  40
  41         else
  42                 spurious_interrupt();
  43 }
  44
  45 static void ar71xx_pci_irq_unmask(unsigned int irq)
  46 {
  47         irq -= AR71XX_PCI_IRQ_BASE;
  48         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
  49                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
  50 }
  51
  52 static void ar71xx_pci_irq_mask(unsigned int irq)
  53 {
  54         irq -= AR71XX_PCI_IRQ_BASE;
  55         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
  56                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
  57 }
  58
  59 static struct irq_chip ar71xx_pci_irq_chip = {
  60         .name           = "AR71XX PCI ",
  61         .mask           = ar71xx_pci_irq_mask,
  62         .unmask         = ar71xx_pci_irq_unmask,
  63         .mask_ack       = ar71xx_pci_irq_mask,
  64 };
  65
  66 static struct irqaction ar71xx_pci_irqaction = {
  67         .handler        = no_action,
  68         .name           = "cascade [AR71XX PCI]",
  69 };
  70
  71 static void __init ar71xx_pci_irq_init(void)
  72 {
  73         int i;
  74
  75         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
  76         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
  77
  78         for (i = AR71XX_PCI_IRQ_BASE;
  79              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
  80                 irq_desc[i].status = IRQ_DISABLED;
  81                 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
  82                                          handle_level_irq);
  83         }
  84
  85         setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
  86 }
  87
  88 #endif /* CONFIG_PCI */
  89
  90 static void ar71xx_gpio_irq_dispatch(void)
  91 {
  92         u32 pending;
  93
  94         pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
  95                 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
  96
  97         if (pending)
  98                 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
  99         else
 100                 spurious_interrupt();
 101 }
 102
 103 static void ar71xx_gpio_irq_unmask(unsigned int irq)
 104 {
 105         irq -= AR71XX_GPIO_IRQ_BASE;
 106         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
 107                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
 108 }
 109
 110 static void ar71xx_gpio_irq_mask(unsigned int irq)
 111 {
 112         irq -= AR71XX_GPIO_IRQ_BASE;
 113         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
 114                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
 115 }
 116
 117 #if 0
 118 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
 119 {
 120         /* TODO: implement */
 121         return 0;
 122 }
 123 #else
 124 #define ar71xx_gpio_irq_set_type        NULL
 125 #endif
 126
 127 struct irq_chip ar71xx_gpio_irq_chip = {
 128         .name           = "AR71XX GPIO",
 129         .unmask         = ar71xx_gpio_irq_unmask,
 130         .mask           = ar71xx_gpio_irq_mask,
 131         .mask_ack       = ar71xx_gpio_irq_mask,
 132         .set_type       = ar71xx_gpio_irq_set_type,
 133 };
 134
 135 static struct irqaction ar71xx_gpio_irqaction = {
 136         .handler        = no_action,
 137         .name           = "cascade [AR71XX GPIO]",
 138 };
 139
 140 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
 141 #define GPIO_INT_ALL    0xffff
 142
 143 static void __init ar71xx_gpio_irq_init(void)
 144 {
 145         int i;
 146
 147         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
 148         ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
 149
 150         /* setup type of all GPIO interrupts to level sensitive */
 151         ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
 152
 153         /* setup polarity of all GPIO interrupts to active high */
 154         ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
 155
 156         for (i = AR71XX_GPIO_IRQ_BASE;
 157              i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
 158                 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
 159                 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
 160                                          handle_level_irq);
 161         }
 162
 163         setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
 164 }
 165
 166 static void ar71xx_misc_irq_dispatch(void)
 167 {
 168         u32 pending;
 169
 170         pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
 171             & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 172
 173         if (pending & MISC_INT_UART)
 174                 do_IRQ(AR71XX_MISC_IRQ_UART);
 175
 176         else if (pending & MISC_INT_DMA)
 177                 do_IRQ(AR71XX_MISC_IRQ_DMA);
 178
 179         else if (pending & MISC_INT_PERFC)
 180                 do_IRQ(AR71XX_MISC_IRQ_PERFC);
 181
 182         else if (pending & MISC_INT_TIMER)
 183                 do_IRQ(AR71XX_MISC_IRQ_TIMER);
 184
 185         else if (pending & MISC_INT_OHCI)
 186                 do_IRQ(AR71XX_MISC_IRQ_OHCI);
 187
 188         else if (pending & MISC_INT_ERROR)
 189                 do_IRQ(AR71XX_MISC_IRQ_ERROR);
 190
 191         else if (pending & MISC_INT_GPIO)
 192                 ar71xx_gpio_irq_dispatch();
 193
 194         else if (pending & MISC_INT_WDOG)
 195                 do_IRQ(AR71XX_MISC_IRQ_WDOG);
 196
 197         else
 198                 spurious_interrupt();
 199 }
 200
 201 static void ar71xx_misc_irq_unmask(unsigned int irq)
 202 {
 203         irq -= AR71XX_MISC_IRQ_BASE;
 204         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 205                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
 206 }
 207
 208 static void ar71xx_misc_irq_mask(unsigned int irq)
 209 {
 210         irq -= AR71XX_MISC_IRQ_BASE;
 211         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 212                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
 213 }
 214
 215 struct irq_chip ar71xx_misc_irq_chip = {
 216         .name           = "AR71XX MISC",
 217         .unmask         = ar71xx_misc_irq_unmask,
 218         .mask           = ar71xx_misc_irq_mask,
 219         .mask_ack       = ar71xx_misc_irq_mask,
 220 };
 221
 222 static struct irqaction ar71xx_misc_irqaction = {
 223         .handler        = no_action,
 224         .name           = "cascade [AR71XX MISC]",
 225 };
 226
 227 static void __init ar71xx_misc_irq_init(void)
 228 {
 229         int i;
 230
 231         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
 232         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
 233
 234         for (i = AR71XX_MISC_IRQ_BASE;
 235              i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
 236                 irq_desc[i].status = IRQ_DISABLED;
 237                 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
 238                                          handle_level_irq);
 239         }
 240
 241         setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
 242 }
 243
 244 asmlinkage void plat_irq_dispatch(void)
 245 {
 246         unsigned long pending;
 247
 248         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 249
 250         if (pending & STATUSF_IP7)
 251                 do_IRQ(AR71XX_CPU_IRQ_TIMER);
 252
 253 #ifdef CONFIG_PCI
 254         else if (pending & STATUSF_IP2)
 255                 ar71xx_pci_irq_dispatch();
 256 #endif
 257
 258         else if (pending & STATUSF_IP4)
 259                 do_IRQ(AR71XX_CPU_IRQ_GE0);
 260
 261         else if (pending & STATUSF_IP5)
 262                 do_IRQ(AR71XX_CPU_IRQ_GE1);
 263
 264         else if (pending & STATUSF_IP3)
 265                 do_IRQ(AR71XX_CPU_IRQ_USB);
 266
 267         else if (pending & STATUSF_IP6)
 268                 ar71xx_misc_irq_dispatch();
 269
 270         else
 271                 spurious_interrupt();
 272 }
 273
 274 void __init arch_init_irq(void)
 275 {
 276         mips_cpu_irq_init();
 277
 278         ar71xx_misc_irq_init();
 279
 280 #ifdef CONFIG_PCI
 281         ar71xx_pci_irq_init();
 282 #endif
 283
 284         ar71xx_gpio_irq_init();
 285 }