ar71xx: add support for ar7241 and ar7242
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ar71xx / irq.c
1 /*
2 * Atheros AR71xx SoC specific interrupt handling
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
21
22 #include <asm/mach-ar71xx/ar71xx.h>
23
24 static void ar71xx_gpio_irq_dispatch(void)
25 {
26 void __iomem *base = ar71xx_gpio_base;
27 u32 pending;
28
29 pending = __raw_readl(base + GPIO_REG_INT_PENDING) &
30 __raw_readl(base + GPIO_REG_INT_ENABLE);
31
32 if (pending)
33 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
34 else
35 spurious_interrupt();
36 }
37
38 static void ar71xx_gpio_irq_unmask(unsigned int irq)
39 {
40 void __iomem *base = ar71xx_gpio_base;
41 u32 t;
42
43 irq -= AR71XX_GPIO_IRQ_BASE;
44
45 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
46 __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE);
47
48 /* flush write */
49 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
50 }
51
52 static void ar71xx_gpio_irq_mask(unsigned int irq)
53 {
54 void __iomem *base = ar71xx_gpio_base;
55 u32 t;
56
57 irq -= AR71XX_GPIO_IRQ_BASE;
58
59 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
60 __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE);
61
62 /* flush write */
63 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
64 }
65
66 #if 0
67 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
68 {
69 /* TODO: implement */
70 return 0;
71 }
72 #else
73 #define ar71xx_gpio_irq_set_type NULL
74 #endif
75
76 static struct irq_chip ar71xx_gpio_irq_chip = {
77 .name = "AR71XX GPIO",
78 .unmask = ar71xx_gpio_irq_unmask,
79 .mask = ar71xx_gpio_irq_mask,
80 .mask_ack = ar71xx_gpio_irq_mask,
81 .set_type = ar71xx_gpio_irq_set_type,
82 };
83
84 static struct irqaction ar71xx_gpio_irqaction = {
85 .handler = no_action,
86 .name = "cascade [AR71XX GPIO]",
87 };
88
89 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
90 #define GPIO_INT_ALL 0xffff
91
92 static void __init ar71xx_gpio_irq_init(void)
93 {
94 void __iomem *base = ar71xx_gpio_base;
95 int i;
96
97 __raw_writel(0, base + GPIO_REG_INT_ENABLE);
98 __raw_writel(0, base + GPIO_REG_INT_PENDING);
99
100 /* setup type of all GPIO interrupts to level sensitive */
101 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE);
102
103 /* setup polarity of all GPIO interrupts to active high */
104 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY);
105
106 for (i = AR71XX_GPIO_IRQ_BASE;
107 i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
108 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
109 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
110 handle_level_irq);
111 }
112
113 setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
114 }
115
116 static void ar71xx_misc_irq_dispatch(void)
117 {
118 u32 pending;
119
120 pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
121 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
122
123 if (pending & MISC_INT_UART)
124 do_IRQ(AR71XX_MISC_IRQ_UART);
125
126 else if (pending & MISC_INT_DMA)
127 do_IRQ(AR71XX_MISC_IRQ_DMA);
128
129 else if (pending & MISC_INT_PERFC)
130 do_IRQ(AR71XX_MISC_IRQ_PERFC);
131
132 else if (pending & MISC_INT_TIMER)
133 do_IRQ(AR71XX_MISC_IRQ_TIMER);
134
135 else if (pending & MISC_INT_OHCI)
136 do_IRQ(AR71XX_MISC_IRQ_OHCI);
137
138 else if (pending & MISC_INT_ERROR)
139 do_IRQ(AR71XX_MISC_IRQ_ERROR);
140
141 else if (pending & MISC_INT_GPIO)
142 ar71xx_gpio_irq_dispatch();
143
144 else if (pending & MISC_INT_WDOG)
145 do_IRQ(AR71XX_MISC_IRQ_WDOG);
146
147 else
148 spurious_interrupt();
149 }
150
151 static void ar71xx_misc_irq_unmask(unsigned int irq)
152 {
153 void __iomem *base = ar71xx_reset_base;
154 u32 t;
155
156 irq -= AR71XX_MISC_IRQ_BASE;
157
158 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
159 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
160
161 /* flush write */
162 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
163 }
164
165 static void ar71xx_misc_irq_mask(unsigned int irq)
166 {
167 void __iomem *base = ar71xx_reset_base;
168 u32 t;
169
170 irq -= AR71XX_MISC_IRQ_BASE;
171
172 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
173 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
174
175 /* flush write */
176 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
177 }
178
179 static void ar724x_misc_irq_ack(unsigned int irq)
180 {
181 void __iomem *base = ar71xx_reset_base;
182 u32 t;
183
184 irq -= AR71XX_MISC_IRQ_BASE;
185
186 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
187 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
188
189 /* flush write */
190 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
191 }
192
193 static struct irq_chip ar71xx_misc_irq_chip = {
194 .name = "AR71XX MISC",
195 .unmask = ar71xx_misc_irq_unmask,
196 .mask = ar71xx_misc_irq_mask,
197 };
198
199 static struct irqaction ar71xx_misc_irqaction = {
200 .handler = no_action,
201 .name = "cascade [AR71XX MISC]",
202 };
203
204 static void __init ar71xx_misc_irq_init(void)
205 {
206 void __iomem *base = ar71xx_reset_base;
207 int i;
208
209 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
210 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
211
212 switch (ar71xx_soc) {
213 case AR71XX_SOC_AR7240:
214 case AR71XX_SOC_AR7241:
215 case AR71XX_SOC_AR7242:
216 ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
217 break;
218 default:
219 ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
220 break;
221 }
222
223 for (i = AR71XX_MISC_IRQ_BASE;
224 i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
225 irq_desc[i].status = IRQ_DISABLED;
226 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
227 handle_level_irq);
228 }
229
230 setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
231 }
232
233 asmlinkage void plat_irq_dispatch(void)
234 {
235 unsigned long pending;
236
237 pending = read_c0_status() & read_c0_cause() & ST0_IM;
238
239 if (pending & STATUSF_IP7)
240 do_IRQ(AR71XX_CPU_IRQ_TIMER);
241
242 else if (pending & STATUSF_IP2)
243 do_IRQ(AR71XX_CPU_IRQ_IP2);
244
245 else if (pending & STATUSF_IP4)
246 do_IRQ(AR71XX_CPU_IRQ_GE0);
247
248 else if (pending & STATUSF_IP5)
249 do_IRQ(AR71XX_CPU_IRQ_GE1);
250
251 else if (pending & STATUSF_IP3)
252 do_IRQ(AR71XX_CPU_IRQ_USB);
253
254 else if (pending & STATUSF_IP6)
255 ar71xx_misc_irq_dispatch();
256
257 else
258 spurious_interrupt();
259 }
260
261 void __init arch_init_irq(void)
262 {
263 mips_cpu_irq_init();
264
265 ar71xx_misc_irq_init();
266
267 cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
268
269 ar71xx_gpio_irq_init();
270 }