target/linux/ar71xx/files/arch/mips/ar71xx/irq.c

   1 /*
   2  *  Atheros AR71xx SoC specific interrupt handling
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18
  19 #include <asm/irq_cpu.h>
  20 #include <asm/mipsregs.h>
  21
  22 #include <asm/mach-ar71xx/ar71xx.h>
  23
  24 static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
  25
  26 #ifdef CONFIG_PCI
  27 static void ar71xx_pci_irq_dispatch(void)
  28 {
  29         u32 pending;
  30
  31         pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
  32                   ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  33
  34         if (pending & PCI_INT_DEV0)
  35                 do_IRQ(AR71XX_PCI_IRQ_DEV0);
  36
  37         else if (pending & PCI_INT_DEV1)
  38                 do_IRQ(AR71XX_PCI_IRQ_DEV1);
  39
  40         else if (pending & PCI_INT_DEV2)
  41                 do_IRQ(AR71XX_PCI_IRQ_DEV2);
  42
  43         else if (pending & PCI_INT_CORE)
  44                 do_IRQ(AR71XX_PCI_IRQ_CORE);
  45
  46         else
  47                 spurious_interrupt();
  48 }
  49
  50 static void ar71xx_pci_irq_unmask(unsigned int irq)
  51 {
  52         irq -= AR71XX_PCI_IRQ_BASE;
  53         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
  54                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
  55
  56         /* flush write */
  57         ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  58 }
  59
  60 static void ar71xx_pci_irq_mask(unsigned int irq)
  61 {
  62         irq -= AR71XX_PCI_IRQ_BASE;
  63         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
  64                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
  65
  66         /* flush write */
  67         ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  68 }
  69
  70 static struct irq_chip ar71xx_pci_irq_chip = {
  71         .name           = "AR71XX PCI ",
  72         .mask           = ar71xx_pci_irq_mask,
  73         .unmask         = ar71xx_pci_irq_unmask,
  74         .mask_ack       = ar71xx_pci_irq_mask,
  75 };
  76
  77 static struct irqaction ar71xx_pci_irqaction = {
  78         .handler        = no_action,
  79         .name           = "cascade [AR71XX PCI]",
  80 };
  81
  82 static void __init ar71xx_pci_irq_init(void)
  83 {
  84         int i;
  85
  86         ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
  87
  88         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
  89         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
  90
  91         for (i = AR71XX_PCI_IRQ_BASE;
  92              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
  93                 irq_desc[i].status = IRQ_DISABLED;
  94                 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
  95                                          handle_level_irq);
  96         }
  97
  98         setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
  99 }
 100
 101 static void ar724x_pci_irq_dispatch(void)
 102 {
 103         u32 pending;
 104
 105         pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) &
 106                   ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 107
 108         if (pending & AR724X_PCI_INT_DEV0)
 109                 do_IRQ(AR71XX_PCI_IRQ_DEV0);
 110
 111         else
 112                 spurious_interrupt();
 113 }
 114
 115 static void ar724x_pci_irq_unmask(unsigned int irq)
 116 {
 117         switch (irq) {
 118         case AR71XX_PCI_IRQ_DEV0:
 119                 irq -= AR71XX_PCI_IRQ_BASE;
 120                 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
 121                               ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) |
 122                                             AR724X_PCI_INT_DEV0);
 123                 /* flush write */
 124                 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 125         }
 126 }
 127
 128 static void ar724x_pci_irq_mask(unsigned int irq)
 129 {
 130         switch (irq) {
 131         case AR71XX_PCI_IRQ_DEV0:
 132                 irq -= AR71XX_PCI_IRQ_BASE;
 133                 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
 134                               ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) &
 135                                             ~AR724X_PCI_INT_DEV0);
 136                 /* flush write */
 137                 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 138
 139                 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS,
 140                               ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) |
 141                                             AR724X_PCI_INT_DEV0);
 142                 /* flush write */
 143                 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS);
 144         }
 145 }
 146
 147 static struct irq_chip ar724x_pci_irq_chip = {
 148         .name           = "AR724X PCI ",
 149         .mask           = ar724x_pci_irq_mask,
 150         .unmask         = ar724x_pci_irq_unmask,
 151         .mask_ack       = ar724x_pci_irq_mask,
 152 };
 153
 154 static struct irqaction ar724x_pci_irqaction = {
 155         .handler        = no_action,
 156         .name           = "cascade [AR724X PCI]",
 157 };
 158
 159 static void __init ar724x_pci_irq_init(void)
 160 {
 161         int i;
 162
 163         ar71xx_ip2_irq_handler = ar724x_pci_irq_dispatch;
 164
 165         ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
 166         ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
 167
 168         for (i = AR71XX_PCI_IRQ_BASE;
 169              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
 170                 irq_desc[i].status = IRQ_DISABLED;
 171                 set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
 172                                          handle_level_irq);
 173         }
 174
 175         setup_irq(AR71XX_CPU_IRQ_PCI, &ar724x_pci_irqaction);
 176 }
 177 #else
 178 static inline void ar71xx_pci_irq_init(void) {};
 179 static inline void ar724x_pci_irq_init(void) {};
 180 #endif /* CONFIG_PCI */
 181
 182 static void ar71xx_gpio_irq_dispatch(void)
 183 {
 184         u32 pending;
 185
 186         pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
 187                 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 188
 189         if (pending)
 190                 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
 191         else
 192                 spurious_interrupt();
 193 }
 194
 195 static void ar71xx_gpio_irq_unmask(unsigned int irq)
 196 {
 197         irq -= AR71XX_GPIO_IRQ_BASE;
 198         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
 199                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
 200
 201         /* flush write */
 202         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 203 }
 204
 205 static void ar71xx_gpio_irq_mask(unsigned int irq)
 206 {
 207         irq -= AR71XX_GPIO_IRQ_BASE;
 208         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
 209                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
 210
 211         /* flush write */
 212         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 213 }
 214
 215 #if 0
 216 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
 217 {
 218         /* TODO: implement */
 219         return 0;
 220 }
 221 #else
 222 #define ar71xx_gpio_irq_set_type        NULL
 223 #endif
 224
 225 static struct irq_chip ar71xx_gpio_irq_chip = {
 226         .name           = "AR71XX GPIO",
 227         .unmask         = ar71xx_gpio_irq_unmask,
 228         .mask           = ar71xx_gpio_irq_mask,
 229         .mask_ack       = ar71xx_gpio_irq_mask,
 230         .set_type       = ar71xx_gpio_irq_set_type,
 231 };
 232
 233 static struct irqaction ar71xx_gpio_irqaction = {
 234         .handler        = no_action,
 235         .name           = "cascade [AR71XX GPIO]",
 236 };
 237
 238 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
 239 #define GPIO_INT_ALL    0xffff
 240
 241 static void __init ar71xx_gpio_irq_init(void)
 242 {
 243         int i;
 244
 245         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
 246         ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
 247
 248         /* setup type of all GPIO interrupts to level sensitive */
 249         ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
 250
 251         /* setup polarity of all GPIO interrupts to active high */
 252         ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
 253
 254         for (i = AR71XX_GPIO_IRQ_BASE;
 255              i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
 256                 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
 257                 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
 258                                          handle_level_irq);
 259         }
 260
 261         setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
 262 }
 263
 264 static void ar71xx_misc_irq_dispatch(void)
 265 {
 266         u32 pending;
 267
 268         pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
 269             & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 270
 271         if (pending & MISC_INT_UART)
 272                 do_IRQ(AR71XX_MISC_IRQ_UART);
 273
 274         else if (pending & MISC_INT_DMA)
 275                 do_IRQ(AR71XX_MISC_IRQ_DMA);
 276
 277         else if (pending & MISC_INT_PERFC)
 278                 do_IRQ(AR71XX_MISC_IRQ_PERFC);
 279
 280         else if (pending & MISC_INT_TIMER)
 281                 do_IRQ(AR71XX_MISC_IRQ_TIMER);
 282
 283         else if (pending & MISC_INT_OHCI)
 284                 do_IRQ(AR71XX_MISC_IRQ_OHCI);
 285
 286         else if (pending & MISC_INT_ERROR)
 287                 do_IRQ(AR71XX_MISC_IRQ_ERROR);
 288
 289         else if (pending & MISC_INT_GPIO)
 290                 ar71xx_gpio_irq_dispatch();
 291
 292         else if (pending & MISC_INT_WDOG)
 293                 do_IRQ(AR71XX_MISC_IRQ_WDOG);
 294
 295         else
 296                 spurious_interrupt();
 297 }
 298
 299 static void ar71xx_misc_irq_unmask(unsigned int irq)
 300 {
 301         irq -= AR71XX_MISC_IRQ_BASE;
 302         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 303                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
 304
 305         /* flush write */
 306         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 307 }
 308
 309 static void ar71xx_misc_irq_mask(unsigned int irq)
 310 {
 311         irq -= AR71XX_MISC_IRQ_BASE;
 312         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 313                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
 314
 315         /* flush write */
 316         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 317 }
 318
 319 static void ar724x_misc_irq_ack(unsigned int irq)
 320 {
 321         irq -= AR71XX_MISC_IRQ_BASE;
 322         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS,
 323                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) & ~(1 << irq));
 324
 325         /* flush write */
 326         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS);
 327 }
 328
 329 static struct irq_chip ar71xx_misc_irq_chip = {
 330         .name           = "AR71XX MISC",
 331         .unmask         = ar71xx_misc_irq_unmask,
 332         .mask           = ar71xx_misc_irq_mask,
 333 };
 334
 335 static struct irqaction ar71xx_misc_irqaction = {
 336         .handler        = no_action,
 337         .name           = "cascade [AR71XX MISC]",
 338 };
 339
 340 static void __init ar71xx_misc_irq_init(void)
 341 {
 342         int i;
 343
 344         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
 345         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
 346
 347         if (ar71xx_soc == AR71XX_SOC_AR7240)
 348                 ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
 349         else
 350                 ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
 351
 352         for (i = AR71XX_MISC_IRQ_BASE;
 353              i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
 354                 irq_desc[i].status = IRQ_DISABLED;
 355                 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
 356                                          handle_level_irq);
 357         }
 358
 359         setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
 360 }
 361
 362 static void ar913x_wmac_irq_dispatch(void)
 363 {
 364         do_IRQ(AR71XX_CPU_IRQ_WMAC);
 365 }
 366
 367 asmlinkage void plat_irq_dispatch(void)
 368 {
 369         unsigned long pending;
 370
 371         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 372
 373         if (pending & STATUSF_IP7)
 374                 do_IRQ(AR71XX_CPU_IRQ_TIMER);
 375
 376         else if (pending & STATUSF_IP2)
 377                 ar71xx_ip2_irq_handler();
 378
 379         else if (pending & STATUSF_IP4)
 380                 do_IRQ(AR71XX_CPU_IRQ_GE0);
 381
 382         else if (pending & STATUSF_IP5)
 383                 do_IRQ(AR71XX_CPU_IRQ_GE1);
 384
 385         else if (pending & STATUSF_IP3)
 386                 do_IRQ(AR71XX_CPU_IRQ_USB);
 387
 388         else if (pending & STATUSF_IP6)
 389                 ar71xx_misc_irq_dispatch();
 390
 391         else
 392                 spurious_interrupt();
 393 }
 394
 395 void __init arch_init_irq(void)
 396 {
 397         mips_cpu_irq_init();
 398
 399         ar71xx_misc_irq_init();
 400
 401         switch (ar71xx_soc) {
 402         case AR71XX_SOC_AR7130:
 403         case AR71XX_SOC_AR7141:
 404         case AR71XX_SOC_AR7161:
 405                 ar71xx_pci_irq_init();
 406                 break;
 407         case AR71XX_SOC_AR7240:
 408                 ar724x_pci_irq_init();
 409                 break;
 410         case AR71XX_SOC_AR9130:
 411         case AR71XX_SOC_AR9132:
 412                 ar71xx_ip2_irq_handler = ar913x_wmac_irq_dispatch;
 413                 break;
 414         default:
 415                 BUG();
 416         }
 417
 418         ar71xx_gpio_irq_init();
 419 }