target/linux/ar71xx/files/arch/mips/ar71xx/irq.c

   1 /*
   2  *  Atheros AR71xx SoC specific interrupt handling
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18
  19 #include <asm/irq_cpu.h>
  20 #include <asm/mipsregs.h>
  21
  22 #include <asm/mach-ar71xx/ar71xx.h>
  23
  24 static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
  25
  26 #ifdef CONFIG_PCI
  27 static void ar71xx_pci_irq_dispatch(void)
  28 {
  29         u32 pending;
  30
  31         pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
  32                   ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  33
  34         if (pending & PCI_INT_DEV0)
  35                 do_IRQ(AR71XX_PCI_IRQ_DEV0);
  36
  37         else if (pending & PCI_INT_DEV1)
  38                 do_IRQ(AR71XX_PCI_IRQ_DEV1);
  39
  40         else if (pending & PCI_INT_DEV2)
  41                 do_IRQ(AR71XX_PCI_IRQ_DEV2);
  42
  43         else if (pending & PCI_INT_CORE)
  44                 do_IRQ(AR71XX_PCI_IRQ_CORE);
  45
  46         else
  47                 spurious_interrupt();
  48 }
  49
  50 static void ar71xx_pci_irq_unmask(unsigned int irq)
  51 {
  52         irq -= AR71XX_PCI_IRQ_BASE;
  53         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
  54                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
  55
  56         /* flush write */
  57         ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  58 }
  59
  60 static void ar71xx_pci_irq_mask(unsigned int irq)
  61 {
  62         irq -= AR71XX_PCI_IRQ_BASE;
  63         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
  64                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
  65
  66         /* flush write */
  67         ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
  68 }
  69
  70 static struct irq_chip ar71xx_pci_irq_chip = {
  71         .name           = "AR71XX PCI ",
  72         .mask           = ar71xx_pci_irq_mask,
  73         .unmask         = ar71xx_pci_irq_unmask,
  74         .mask_ack       = ar71xx_pci_irq_mask,
  75 };
  76
  77 static struct irqaction ar71xx_pci_irqaction = {
  78         .handler        = no_action,
  79         .name           = "cascade [AR71XX PCI]",
  80 };
  81
  82 static void __init ar71xx_pci_irq_init(void)
  83 {
  84         int i;
  85
  86         ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
  87
  88         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
  89         ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
  90
  91         for (i = AR71XX_PCI_IRQ_BASE;
  92              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
  93                 irq_desc[i].status = IRQ_DISABLED;
  94                 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
  95                                          handle_level_irq);
  96         }
  97
  98         setup_irq(AR71XX_CPU_IRQ_IP2, &ar71xx_pci_irqaction);
  99 }
 100
 101 static void ar724x_pci_irq_dispatch(void)
 102 {
 103         u32 pending;
 104
 105         pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) &
 106                   ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 107
 108         if (pending & AR724X_PCI_INT_DEV0)
 109                 do_IRQ(AR71XX_PCI_IRQ_DEV0);
 110
 111         else
 112                 spurious_interrupt();
 113 }
 114
 115 static void ar724x_pci_irq_unmask(unsigned int irq)
 116 {
 117         switch (irq) {
 118         case AR71XX_PCI_IRQ_DEV0:
 119                 irq -= AR71XX_PCI_IRQ_BASE;
 120                 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
 121                               ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) |
 122                                             AR724X_PCI_INT_DEV0);
 123                 /* flush write */
 124                 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 125         }
 126 }
 127
 128 static void ar724x_pci_irq_mask(unsigned int irq)
 129 {
 130         switch (irq) {
 131         case AR71XX_PCI_IRQ_DEV0:
 132                 irq -= AR71XX_PCI_IRQ_BASE;
 133                 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
 134                               ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) &
 135                                             ~AR724X_PCI_INT_DEV0);
 136                 /* flush write */
 137                 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 138
 139                 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS,
 140                               ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) |
 141                                             AR724X_PCI_INT_DEV0);
 142                 /* flush write */
 143                 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS);
 144         }
 145 }
 146
 147 static struct irq_chip ar724x_pci_irq_chip = {
 148         .name           = "AR724X PCI ",
 149         .mask           = ar724x_pci_irq_mask,
 150         .unmask         = ar724x_pci_irq_unmask,
 151         .mask_ack       = ar724x_pci_irq_mask,
 152 };
 153
 154 static struct irqaction ar724x_pci_irqaction = {
 155         .handler        = no_action,
 156         .name           = "cascade [AR724X PCI]",
 157 };
 158
 159 static void __init ar724x_pci_irq_init(void)
 160 {
 161         u32 t;
 162         int i;
 163
 164         t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
 165         if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY |
 166                  AR724X_RESET_PCIE_PHY_SERIAL)) {
 167                 return;
 168         }
 169
 170         ar71xx_ip2_irq_handler = ar724x_pci_irq_dispatch;
 171
 172         ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
 173         ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
 174
 175         for (i = AR71XX_PCI_IRQ_BASE;
 176              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
 177                 irq_desc[i].status = IRQ_DISABLED;
 178                 set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
 179                                          handle_level_irq);
 180         }
 181
 182         setup_irq(AR71XX_CPU_IRQ_IP2, &ar724x_pci_irqaction);
 183 }
 184 #else
 185 static inline void ar71xx_pci_irq_init(void) {};
 186 static inline void ar724x_pci_irq_init(void) {};
 187 #endif /* CONFIG_PCI */
 188
 189 static void ar71xx_gpio_irq_dispatch(void)
 190 {
 191         u32 pending;
 192
 193         pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
 194                 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 195
 196         if (pending)
 197                 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
 198         else
 199                 spurious_interrupt();
 200 }
 201
 202 static void ar71xx_gpio_irq_unmask(unsigned int irq)
 203 {
 204         irq -= AR71XX_GPIO_IRQ_BASE;
 205         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
 206                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
 207
 208         /* flush write */
 209         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 210 }
 211
 212 static void ar71xx_gpio_irq_mask(unsigned int irq)
 213 {
 214         irq -= AR71XX_GPIO_IRQ_BASE;
 215         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
 216                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
 217
 218         /* flush write */
 219         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
 220 }
 221
 222 #if 0
 223 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
 224 {
 225         /* TODO: implement */
 226         return 0;
 227 }
 228 #else
 229 #define ar71xx_gpio_irq_set_type        NULL
 230 #endif
 231
 232 static struct irq_chip ar71xx_gpio_irq_chip = {
 233         .name           = "AR71XX GPIO",
 234         .unmask         = ar71xx_gpio_irq_unmask,
 235         .mask           = ar71xx_gpio_irq_mask,
 236         .mask_ack       = ar71xx_gpio_irq_mask,
 237         .set_type       = ar71xx_gpio_irq_set_type,
 238 };
 239
 240 static struct irqaction ar71xx_gpio_irqaction = {
 241         .handler        = no_action,
 242         .name           = "cascade [AR71XX GPIO]",
 243 };
 244
 245 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
 246 #define GPIO_INT_ALL    0xffff
 247
 248 static void __init ar71xx_gpio_irq_init(void)
 249 {
 250         int i;
 251
 252         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
 253         ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
 254
 255         /* setup type of all GPIO interrupts to level sensitive */
 256         ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
 257
 258         /* setup polarity of all GPIO interrupts to active high */
 259         ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
 260
 261         for (i = AR71XX_GPIO_IRQ_BASE;
 262              i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
 263                 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
 264                 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
 265                                          handle_level_irq);
 266         }
 267
 268         setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
 269 }
 270
 271 static void ar71xx_misc_irq_dispatch(void)
 272 {
 273         u32 pending;
 274
 275         pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
 276             & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 277
 278         if (pending & MISC_INT_UART)
 279                 do_IRQ(AR71XX_MISC_IRQ_UART);
 280
 281         else if (pending & MISC_INT_DMA)
 282                 do_IRQ(AR71XX_MISC_IRQ_DMA);
 283
 284         else if (pending & MISC_INT_PERFC)
 285                 do_IRQ(AR71XX_MISC_IRQ_PERFC);
 286
 287         else if (pending & MISC_INT_TIMER)
 288                 do_IRQ(AR71XX_MISC_IRQ_TIMER);
 289
 290         else if (pending & MISC_INT_OHCI)
 291                 do_IRQ(AR71XX_MISC_IRQ_OHCI);
 292
 293         else if (pending & MISC_INT_ERROR)
 294                 do_IRQ(AR71XX_MISC_IRQ_ERROR);
 295
 296         else if (pending & MISC_INT_GPIO)
 297                 ar71xx_gpio_irq_dispatch();
 298
 299         else if (pending & MISC_INT_WDOG)
 300                 do_IRQ(AR71XX_MISC_IRQ_WDOG);
 301
 302         else
 303                 spurious_interrupt();
 304 }
 305
 306 static void ar71xx_misc_irq_unmask(unsigned int irq)
 307 {
 308         irq -= AR71XX_MISC_IRQ_BASE;
 309         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 310                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
 311
 312         /* flush write */
 313         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 314 }
 315
 316 static void ar71xx_misc_irq_mask(unsigned int irq)
 317 {
 318         irq -= AR71XX_MISC_IRQ_BASE;
 319         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 320                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
 321
 322         /* flush write */
 323         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 324 }
 325
 326 static void ar724x_misc_irq_ack(unsigned int irq)
 327 {
 328         irq -= AR71XX_MISC_IRQ_BASE;
 329         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS,
 330                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) & ~(1 << irq));
 331
 332         /* flush write */
 333         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS);
 334 }
 335
 336 static struct irq_chip ar71xx_misc_irq_chip = {
 337         .name           = "AR71XX MISC",
 338         .unmask         = ar71xx_misc_irq_unmask,
 339         .mask           = ar71xx_misc_irq_mask,
 340 };
 341
 342 static struct irqaction ar71xx_misc_irqaction = {
 343         .handler        = no_action,
 344         .name           = "cascade [AR71XX MISC]",
 345 };
 346
 347 static void __init ar71xx_misc_irq_init(void)
 348 {
 349         int i;
 350
 351         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
 352         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
 353
 354         if (ar71xx_soc == AR71XX_SOC_AR7240)
 355                 ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
 356         else
 357                 ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
 358
 359         for (i = AR71XX_MISC_IRQ_BASE;
 360              i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
 361                 irq_desc[i].status = IRQ_DISABLED;
 362                 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
 363                                          handle_level_irq);
 364         }
 365
 366         setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
 367 }
 368
 369 static void ar913x_wmac_irq_dispatch(void)
 370 {
 371         do_IRQ(AR71XX_CPU_IRQ_IP2);
 372 }
 373
 374 asmlinkage void plat_irq_dispatch(void)
 375 {
 376         unsigned long pending;
 377
 378         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 379
 380         if (pending & STATUSF_IP7)
 381                 do_IRQ(AR71XX_CPU_IRQ_TIMER);
 382
 383         else if (pending & STATUSF_IP2)
 384                 ar71xx_ip2_irq_handler();
 385
 386         else if (pending & STATUSF_IP4)
 387                 do_IRQ(AR71XX_CPU_IRQ_GE0);
 388
 389         else if (pending & STATUSF_IP5)
 390                 do_IRQ(AR71XX_CPU_IRQ_GE1);
 391
 392         else if (pending & STATUSF_IP3)
 393                 do_IRQ(AR71XX_CPU_IRQ_USB);
 394
 395         else if (pending & STATUSF_IP6)
 396                 ar71xx_misc_irq_dispatch();
 397
 398         else
 399                 spurious_interrupt();
 400 }
 401
 402 void __init arch_init_irq(void)
 403 {
 404         mips_cpu_irq_init();
 405
 406         ar71xx_misc_irq_init();
 407
 408         cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
 409
 410         switch (ar71xx_soc) {
 411         case AR71XX_SOC_AR7130:
 412         case AR71XX_SOC_AR7141:
 413         case AR71XX_SOC_AR7161:
 414                 ar71xx_pci_irq_init();
 415                 break;
 416         case AR71XX_SOC_AR7240:
 417                 ar724x_pci_irq_init();
 418                 break;
 419         case AR71XX_SOC_AR9130:
 420         case AR71XX_SOC_AR9132:
 421                 ar71xx_ip2_irq_handler = ar913x_wmac_irq_dispatch;
 422                 break;
 423         default:
 424                 BUG();
 425         }
 426
 427         ar71xx_gpio_irq_init();
 428 }