target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c

   1 /*
   2  *  Atheros PB42 board support
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/bitops.h>
  14 #include <linux/input.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/spi/flash.h>
  18
  19 #include <asm/mips_machine.h>
  20 #include <asm/mach-ar71xx/ar71xx.h>
  21 #include <asm/mach-ar71xx/pci.h>
  22
  23 #include "devices.h"
  24
  25 #define PB42_BUTTONS_POLL_INTERVAL      20
  26
  27 #define PB42_GPIO_BTN_SW4       8
  28 #define PB42_GPIO_BTN_SW5       3
  29
  30 static struct spi_board_info pb42_spi_info[] = {
  31         {
  32                 .bus_num        = 0,
  33                 .chip_select    = 0,
  34                 .max_speed_hz   = 25000000,
  35                 .modalias       = "m25p80",
  36         }
  37 };
  38
  39 static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = {
  40         {
  41                 .slot   = 0,
  42                 .pin    = 1,
  43                 .irq    = AR71XX_PCI_IRQ_DEV0,
  44         }, {
  45                 .slot   = 1,
  46                 .pin    = 1,
  47                 .irq    = AR71XX_PCI_IRQ_DEV1,
  48         }, {
  49                 .slot   = 2,
  50                 .pin    = 1,
  51                 .irq    = AR71XX_PCI_IRQ_DEV2,
  52         }
  53 };
  54
  55 static struct gpio_button pb42_gpio_buttons[] __initdata = {
  56         {
  57                 .desc           = "sw4",
  58                 .type           = EV_KEY,
  59                 .code           = BTN_0,
  60                 .threshold      = 5,
  61                 .gpio           = PB42_GPIO_BTN_SW4,
  62                 .active_low     = 1,
  63         } , {
  64                 .desc           = "sw5",
  65                 .type           = EV_KEY,
  66                 .code           = BTN_1,
  67                 .threshold      = 5,
  68                 .gpio           = PB42_GPIO_BTN_SW5,
  69                 .active_low     = 1,
  70         }
  71 };
  72
  73 #define PB42_WAN_PHYMASK        BIT(20)
  74 #define PB42_LAN_PHYMASK        (BIT(16) | BIT(17) | BIT(18) | BIT(19))
  75 #define PB42_MDIO_PHYMASK       (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK)
  76
  77 static void __init pb42_init(void)
  78 {
  79         ar71xx_add_device_spi(NULL, pb42_spi_info,
  80                                 ARRAY_SIZE(pb42_spi_info));
  81
  82         ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK);
  83
  84         ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  85         ar71xx_eth0_data.phy_mask = PB42_WAN_PHYMASK;
  86
  87         ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  88         ar71xx_eth1_data.phy_mask = PB42_LAN_PHYMASK;
  89         ar71xx_eth1_data.speed = SPEED_100;
  90         ar71xx_eth1_data.duplex = DUPLEX_FULL;
  91
  92         ar71xx_add_device_eth(0);
  93         ar71xx_add_device_eth(1);
  94
  95         ar71xx_add_device_gpio_buttons(-1, PB42_BUTTONS_POLL_INTERVAL,
  96                                        ARRAY_SIZE(pb42_gpio_buttons),
  97                                        pb42_gpio_buttons);
  98
  99         ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs);
 100 }
 101
 102 MIPS_MACHINE(AR71XX_MACH_PB42, "Atheros PB42", pb42_init);