target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb92.c

   1 /*
   2  *  Atheros PB92 board support
   3  *
   4  *  Copyright (C) 2010 Felix Fietkau <nbd@openwrt.org>
   5  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/mtd/mtd.h>
  14 #include <linux/mtd/partitions.h>
  15 #include <asm/mach-ar71xx/ar71xx.h>
  16
  17 #include "machtype.h"
  18 #include "devices.h"
  19 #include "dev-m25p80.h"
  20 #include "dev-gpio-buttons.h"
  21 #include "dev-pb9x-pci.h"
  22 #include "dev-usb.h"
  23
  24 #ifdef CONFIG_MTD_PARTITIONS
  25 static struct mtd_partition pb92_partitions[] = {
  26         {
  27                 .name           = "u-boot",
  28                 .offset         = 0,
  29                 .size           = 0x040000,
  30                 .mask_flags     = MTD_WRITEABLE,
  31         }, {
  32                 .name           = "u-boot-env",
  33                 .offset         = 0x040000,
  34                 .size           = 0x010000,
  35         }, {
  36                 .name           = "rootfs",
  37                 .offset         = 0x050000,
  38                 .size           = 0x2b0000,
  39         }, {
  40                 .name           = "uImage",
  41                 .offset         = 0x300000,
  42                 .size           = 0x0e0000,
  43         }, {
  44                 .name           = "ART",
  45                 .offset         = 0x3e0000,
  46                 .size           = 0x020000,
  47                 .mask_flags     = MTD_WRITEABLE,
  48         }
  49 };
  50 #endif /* CONFIG_MTD_PARTITIONS */
  51
  52 static struct flash_platform_data pb92_flash_data = {
  53 #ifdef CONFIG_MTD_PARTITIONS
  54         .parts          = pb92_partitions,
  55         .nr_parts       = ARRAY_SIZE(pb92_partitions),
  56 #endif
  57 };
  58
  59 #define PB92_KEYS_POLL_INTERVAL         20      /* msecs */
  60 #define PB92_KEYS_DEBOUNCE_INTERVAL     (3 * PB92_KEYS_POLL_INTERVAL)
  61
  62 #define PB92_GPIO_BTN_SW4       8
  63 #define PB92_GPIO_BTN_SW5       3
  64
  65 static struct gpio_keys_button pb92_gpio_keys[] __initdata = {
  66         {
  67                 .desc           = "sw4",
  68                 .type           = EV_KEY,
  69                 .code           = BTN_0,
  70                 .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL,
  71                 .gpio           = PB92_GPIO_BTN_SW4,
  72                 .active_low     = 1,
  73         }, {
  74                 .desc           = "sw5",
  75                 .type           = EV_KEY,
  76                 .code           = BTN_1,
  77                 .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL,
  78                 .gpio           = PB92_GPIO_BTN_SW5,
  79                 .active_low     = 1,
  80         }
  81 };
  82
  83 static void __init pb92_init(void)
  84 {
  85         u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
  86
  87         ar71xx_add_device_m25p80(&pb92_flash_data);
  88
  89         ar71xx_add_device_mdio(~BIT(0));
  90         ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0);
  91         ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  92         ar71xx_eth0_data.speed = SPEED_1000;
  93         ar71xx_eth0_data.duplex = DUPLEX_FULL;
  94         ar71xx_eth0_data.phy_mask = BIT(0);
  95
  96         ar71xx_add_device_eth(0);
  97
  98         ar71xx_register_gpio_keys_polled(-1, PB92_KEYS_POLL_INTERVAL,
  99                                          ARRAY_SIZE(pb92_gpio_keys),
 100                                          pb92_gpio_keys);
 101
 102         pb9x_pci_init();
 103 }
 104
 105 MIPS_MACHINE(AR71XX_MACH_PB92, "PB92", "Atheros PB92", pb92_init);