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[ar71xx] ag71xx: introduce SoC specific fuctions for DDR flush and PLL setup
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ar71xx / platform.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/platform_device.h>
19 #include <linux/serial_8250.h>
20
21 #include <asm/mips_machine.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
23 #include <asm/mach-ar71xx/platform.h>
24
25 static u8 ar71xx_mac_base[ETH_ALEN] __initdata;
26
27 /*
28 * OHCI (USB full speed host controller)
29 */
30 static struct resource ar71xx_usb_ohci_resources[] = {
31 [0] = {
32 .start = AR71XX_OHCI_BASE,
33 .end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1,
34 .flags = IORESOURCE_MEM,
35 },
36 [1] = {
37 .start = AR71XX_MISC_IRQ_OHCI,
38 .end = AR71XX_MISC_IRQ_OHCI,
39 .flags = IORESOURCE_IRQ,
40 },
41 };
42
43 static u64 ar71xx_ohci_dmamask = DMA_BIT_MASK(32);
44 static struct platform_device ar71xx_usb_ohci_device = {
45 .name = "ar71xx-ohci",
46 .id = -1,
47 .resource = ar71xx_usb_ohci_resources,
48 .num_resources = ARRAY_SIZE(ar71xx_usb_ohci_resources),
49 .dev = {
50 .dma_mask = &ar71xx_ohci_dmamask,
51 .coherent_dma_mask = DMA_BIT_MASK(32),
52 },
53 };
54
55 /*
56 * EHCI (USB full speed host controller)
57 */
58 static struct resource ar71xx_usb_ehci_resources[] = {
59 [0] = {
60 .start = AR71XX_EHCI_BASE,
61 .end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1,
62 .flags = IORESOURCE_MEM,
63 },
64 [1] = {
65 .start = AR71XX_CPU_IRQ_USB,
66 .end = AR71XX_CPU_IRQ_USB,
67 .flags = IORESOURCE_IRQ,
68 },
69 };
70
71 static u64 ar71xx_ehci_dmamask = DMA_BIT_MASK(32);
72 static struct platform_device ar71xx_usb_ehci_device = {
73 .name = "ar71xx-ehci",
74 .id = -1,
75 .resource = ar71xx_usb_ehci_resources,
76 .num_resources = ARRAY_SIZE(ar71xx_usb_ehci_resources),
77 .dev = {
78 .dma_mask = &ar71xx_ehci_dmamask,
79 .coherent_dma_mask = DMA_BIT_MASK(32),
80 },
81 };
82
83 #define AR71XX_USB_RESET_MASK \
84 (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \
85 | RESET_MODULE_USB_OHCI_DLL)
86
87 void __init ar71xx_add_device_usb(void)
88 {
89 ar71xx_device_stop(AR71XX_USB_RESET_MASK);
90 mdelay(1000);
91 ar71xx_device_start(AR71XX_USB_RESET_MASK);
92
93 /* Turning on the Buff and Desc swap bits */
94 ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG, 0xf0000);
95
96 /* WAR for HW bug. Here it adjusts the duration between two SOFS */
97 ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x20c00);
98
99 mdelay(900);
100
101 platform_device_register(&ar71xx_usb_ohci_device);
102 platform_device_register(&ar71xx_usb_ehci_device);
103 }
104
105 #ifdef CONFIG_AR71XX_EARLY_SERIAL
106 static void __init ar71xx_add_device_uart(void) {};
107 #else
108 static struct resource ar71xx_uart_resources[] = {
109 {
110 .start = AR71XX_UART_BASE,
111 .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
112 .flags = IORESOURCE_MEM,
113 },
114 };
115
116 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
117 static struct plat_serial8250_port ar71xx_uart_data[] = {
118 {
119 .mapbase = AR71XX_UART_BASE,
120 .irq = AR71XX_MISC_IRQ_UART,
121 .flags = AR71XX_UART_FLAGS,
122 .iotype = UPIO_MEM32,
123 .regshift = 2,
124 }, {
125 /* terminating entry */
126 }
127 };
128
129 static struct platform_device ar71xx_uart_device = {
130 .name = "serial8250",
131 .id = PLAT8250_DEV_PLATFORM,
132 .resource = ar71xx_uart_resources,
133 .num_resources = ARRAY_SIZE(ar71xx_uart_resources),
134 .dev = {
135 .platform_data = ar71xx_uart_data
136 },
137 };
138
139 static void __init ar71xx_add_device_uart(void)
140 {
141 ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
142 platform_device_register(&ar71xx_uart_device);
143 }
144 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
145
146 static struct resource ar71xx_mdio_resources[] = {
147 {
148 .name = "mdio_base",
149 .flags = IORESOURCE_MEM,
150 .start = AR71XX_GE0_BASE + 0x20,
151 .end = AR71XX_GE0_BASE + 0x38 - 1,
152 }
153 };
154
155 static struct ag71xx_mdio_platform_data ar71xx_mdio_data = {
156 .phy_mask = 0xffffffff,
157 };
158
159 static struct platform_device ar71xx_mdio_device = {
160 .name = "ag71xx-mdio",
161 .id = -1,
162 .resource = ar71xx_mdio_resources,
163 .num_resources = ARRAY_SIZE(ar71xx_mdio_resources),
164 .dev = {
165 .platform_data = &ar71xx_mdio_data,
166 },
167 };
168
169 void __init ar71xx_add_device_mdio(u32 phy_mask)
170 {
171 ar71xx_mdio_data.phy_mask = phy_mask;
172 platform_device_register(&ar71xx_mdio_device);
173 }
174
175 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
176 {
177 void __iomem *base;
178 u32 t;
179
180 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
181
182 t = __raw_readl(base + cfg_reg);
183 t &= ~(3 << shift);
184 t |= (2 << shift);
185 __raw_writel(t, base + cfg_reg);
186 udelay(100);
187
188 __raw_writel(pll_val, base + pll_reg);
189
190 t |= (3 << shift);
191 __raw_writel(t, base + cfg_reg);
192 udelay(100);
193
194 t &= ~(3 << shift);
195 __raw_writel(t, base + cfg_reg);
196 udelay(100);
197
198 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
199 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
200
201 iounmap(base);
202 }
203
204 static void ar71xx_set_pll_ge0(u32 val)
205 {
206 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
207 val, AR71XX_ETH0_PLL_SHIFT);
208 }
209
210 static void ar71xx_set_pll_ge1(u32 val)
211 {
212 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
213 val, AR71XX_ETH1_PLL_SHIFT);
214 }
215
216 static void ar91xx_set_pll_ge0(u32 val)
217 {
218 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
219 val, AR91XX_ETH0_PLL_SHIFT);
220 }
221
222 static void ar91xx_set_pll_ge1(u32 val)
223 {
224 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
225 val, AR91XX_ETH1_PLL_SHIFT);
226 }
227
228 static void ar71xx_ddr_flush_ge0(void)
229 {
230 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
231 }
232
233 static void ar71xx_ddr_flush_ge1(void)
234 {
235 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
236 }
237
238 static void ar91xx_ddr_flush_ge0(void)
239 {
240 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
241 }
242
243 static void ar91xx_ddr_flush_ge1(void)
244 {
245 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
246 }
247
248 static struct resource ar71xx_eth0_resources[] = {
249 {
250 .name = "mac_base",
251 .flags = IORESOURCE_MEM,
252 .start = AR71XX_GE0_BASE,
253 .end = AR71XX_GE0_BASE + 0x20 - 1,
254 }, {
255 .name = "mac_base2",
256 .flags = IORESOURCE_MEM,
257 .start = AR71XX_GE0_BASE + 0x38,
258 .end = AR71XX_GE0_BASE + 0x200 - 1,
259 }, {
260 .name = "mii_ctrl",
261 .flags = IORESOURCE_MEM,
262 .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL,
263 .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
264 }, {
265 .name = "mac_irq",
266 .flags = IORESOURCE_IRQ,
267 .start = AR71XX_CPU_IRQ_GE0,
268 .end = AR71XX_CPU_IRQ_GE0,
269 },
270 };
271
272 struct ag71xx_platform_data ar71xx_eth0_data = {
273 .reset_bit = RESET_MODULE_GE0_MAC,
274 };
275
276 static struct platform_device ar71xx_eth0_device = {
277 .name = "ag71xx",
278 .id = 0,
279 .resource = ar71xx_eth0_resources,
280 .num_resources = ARRAY_SIZE(ar71xx_eth0_resources),
281 .dev = {
282 .platform_data = &ar71xx_eth0_data,
283 },
284 };
285
286 static struct resource ar71xx_eth1_resources[] = {
287 {
288 .name = "mac_base",
289 .flags = IORESOURCE_MEM,
290 .start = AR71XX_GE1_BASE,
291 .end = AR71XX_GE1_BASE + 0x20 - 1,
292 }, {
293 .name = "mac_base2",
294 .flags = IORESOURCE_MEM,
295 .start = AR71XX_GE1_BASE + 0x38,
296 .end = AR71XX_GE1_BASE + 0x200 - 1,
297 }, {
298 .name = "mii_ctrl",
299 .flags = IORESOURCE_MEM,
300 .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL,
301 .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
302 }, {
303 .name = "mac_irq",
304 .flags = IORESOURCE_IRQ,
305 .start = AR71XX_CPU_IRQ_GE1,
306 .end = AR71XX_CPU_IRQ_GE1,
307 },
308 };
309
310 struct ag71xx_platform_data ar71xx_eth1_data = {
311 .reset_bit = RESET_MODULE_GE1_MAC,
312 };
313
314 static struct platform_device ar71xx_eth1_device = {
315 .name = "ag71xx",
316 .id = 1,
317 .resource = ar71xx_eth1_resources,
318 .num_resources = ARRAY_SIZE(ar71xx_eth1_resources),
319 .dev = {
320 .platform_data = &ar71xx_eth1_data,
321 },
322 };
323
324 static int ar71xx_eth_instance __initdata;
325 void __init ar71xx_add_device_eth(unsigned int id)
326 {
327 struct platform_device *pdev;
328 struct ag71xx_platform_data *pdata;
329
330 switch (id) {
331 case 0:
332 switch (ar71xx_eth0_data.phy_if_mode) {
333 case PHY_INTERFACE_MODE_MII:
334 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII;
335 break;
336 case PHY_INTERFACE_MODE_GMII:
337 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII;
338 break;
339 case PHY_INTERFACE_MODE_RGMII:
340 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII;
341 break;
342 case PHY_INTERFACE_MODE_RMII:
343 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII;
344 break;
345 default:
346 printk(KERN_ERR "ar71xx: invalid PHY interface mode "
347 "for eth0\n");
348 return;
349 }
350 pdev = &ar71xx_eth0_device;
351 break;
352 case 1:
353 switch (ar71xx_eth1_data.phy_if_mode) {
354 case PHY_INTERFACE_MODE_RMII:
355 ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII;
356 break;
357 case PHY_INTERFACE_MODE_RGMII:
358 ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII;
359 break;
360 default:
361 printk(KERN_ERR "ar71xx: invalid PHY interface mode "
362 "for eth1\n");
363 return;
364 }
365 pdev = &ar71xx_eth1_device;
366 break;
367 default:
368 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
369 return;
370 }
371
372 pdata = pdev->dev.platform_data;
373
374 switch (ar71xx_soc) {
375 case AR71XX_SOC_AR7130:
376 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
377 : ar71xx_ddr_flush_ge0;
378 pdata->set_pll = id ? ar71xx_set_pll_ge1
379 : ar71xx_set_pll_ge0;
380 break;
381
382 case AR71XX_SOC_AR7141:
383 case AR71XX_SOC_AR7161:
384 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
385 : ar71xx_ddr_flush_ge0;
386 pdata->set_pll = id ? ar71xx_set_pll_ge1
387 : ar71xx_set_pll_ge0;
388 pdata->has_gbit = 1;
389 break;
390
391 case AR71XX_SOC_AR9130:
392 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
393 : ar91xx_ddr_flush_ge0;
394 pdata->set_pll = id ? ar91xx_set_pll_ge1
395 : ar91xx_set_pll_ge0;
396 break;
397
398 case AR71XX_SOC_AR9132:
399 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
400 : ar91xx_ddr_flush_ge0;
401 pdata->set_pll = id ? ar91xx_set_pll_ge1
402 : ar91xx_set_pll_ge0;
403 pdata->has_gbit = 1;
404 break;
405
406 default:
407 BUG();
408 }
409
410 switch (pdata->phy_if_mode) {
411 case PHY_INTERFACE_MODE_GMII:
412 case PHY_INTERFACE_MODE_RGMII:
413 if (!pdata->has_gbit) {
414 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
415 id);
416 return;
417 }
418 /* fallthrough */
419 default:
420 break;
421 }
422
423 memcpy(pdata->mac_addr, ar71xx_mac_base, ETH_ALEN);
424 pdata->mac_addr[5] += ar71xx_eth_instance;
425
426 platform_device_register(pdev);
427 ar71xx_eth_instance++;
428 }
429
430 static struct resource ar71xx_spi_resources[] = {
431 [0] = {
432 .start = AR71XX_SPI_BASE,
433 .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
434 .flags = IORESOURCE_MEM,
435 },
436 };
437
438 static struct platform_device ar71xx_spi_device = {
439 .name = "ar71xx-spi",
440 .id = -1,
441 .resource = ar71xx_spi_resources,
442 .num_resources = ARRAY_SIZE(ar71xx_spi_resources),
443 };
444
445 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
446 struct spi_board_info const *info,
447 unsigned n)
448 {
449 ar71xx_gpio_function_enable(GPIO_FUNC_SPI_EN);
450
451 spi_register_board_info(info, n);
452 ar71xx_spi_device.dev.platform_data = pdata;
453 platform_device_register(&ar71xx_spi_device);
454 }
455
456 void __init ar71xx_add_device_leds_gpio(int id, unsigned num_leds,
457 struct gpio_led *leds)
458 {
459 struct platform_device *pdev;
460 struct gpio_led_platform_data pdata;
461 struct gpio_led *p;
462 int err;
463
464 p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
465 if (!p)
466 return;
467
468 memcpy(p, leds, num_leds * sizeof(*p));
469
470 pdev = platform_device_alloc("leds-gpio", id);
471 if (!pdev)
472 goto err_free_leds;
473
474 memset(&pdata, 0, sizeof(pdata));
475 pdata.num_leds = num_leds;
476 pdata.leds = leds;
477
478 err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
479 if (err)
480 goto err_put_pdev;
481
482 err = platform_device_add(pdev);
483 if (err)
484 goto err_put_pdev;
485
486 return;
487
488 err_put_pdev:
489 platform_device_put(pdev);
490
491 err_free_leds:
492 kfree(p);
493 }
494
495 void __init ar71xx_add_device_gpio_buttons(int id,
496 unsigned poll_interval,
497 unsigned nbuttons,
498 struct gpio_button *buttons)
499 {
500 struct platform_device *pdev;
501 struct gpio_buttons_platform_data pdata;
502 struct gpio_button *p;
503 int err;
504
505 p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL);
506 if (!p)
507 return;
508
509 memcpy(p, buttons, nbuttons * sizeof(*p));
510
511 pdev = platform_device_alloc("gpio-buttons", id);
512 if (!pdev)
513 goto err_free_buttons;
514
515 memset(&pdata, 0, sizeof(pdata));
516 pdata.poll_interval = poll_interval;
517 pdata.nbuttons = nbuttons;
518 pdata.buttons = p;
519
520 err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
521 if (err)
522 goto err_put_pdev;
523
524
525 err = platform_device_add(pdev);
526 if (err)
527 goto err_put_pdev;
528
529 return;
530
531 err_put_pdev:
532 platform_device_put(pdev);
533
534 err_free_buttons:
535 kfree(p);
536 }
537
538 void __init ar71xx_add_device_wdt(void)
539 {
540 platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
541 }
542
543 void __init ar71xx_set_mac_base(unsigned char *mac)
544 {
545 memcpy(ar71xx_mac_base, mac, ETH_ALEN);
546 }
547
548 void __init ar71xx_parse_mac_addr(char *mac_str)
549 {
550 u8 tmp[ETH_ALEN];
551 int t;
552
553 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
554 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
555
556 if (t == ETH_ALEN)
557 ar71xx_set_mac_base(tmp);
558 else
559 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
560 "\"%s\"\n", mac_str);
561 }
562
563 static int __init ar71xx_machine_setup(void)
564 {
565 ar71xx_gpio_init();
566
567 ar71xx_add_device_uart();
568 ar71xx_add_device_wdt();
569
570 mips_machine_setup();
571 return 0;
572 }
573
574 arch_initcall(ar71xx_machine_setup);
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