target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros 2.6.15 BSP
   9  *  Parts of this file are based on Atheros 2.6.31 BSP
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/bootmem.h>
  19
  20 #include <asm/bootinfo.h>
  21 #include <asm/time.h>           /* for mips_hpt_frequency */
  22 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  23 #include <asm/mips_machine.h>
  24
  25 #include <asm/mach-ar71xx/ar71xx.h>
  26
  27 #include "machtype.h"
  28 #include "devices.h"
  29
  30 #define AR71XX_SYS_TYPE_LEN     64
  31 #define AR71XX_BASE_FREQ        40000000
  32 #define AR91XX_BASE_FREQ        5000000
  33 #define AR724X_BASE_FREQ        5000000
  34
  35 u32 ar71xx_cpu_freq;
  36 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  37
  38 u32 ar71xx_ahb_freq;
  39 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  40
  41 u32 ar71xx_ddr_freq;
  42 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  43
  44 u32 ar934x_ref_freq;
  45 EXPORT_SYMBOL_GPL(ar934x_ref_freq);
  46
  47 enum ar71xx_soc_type ar71xx_soc;
  48 EXPORT_SYMBOL_GPL(ar71xx_soc);
  49
  50 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  51
  52 static void ar71xx_restart(char *command)
  53 {
  54         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  55         for (;;)
  56                 if (cpu_wait)
  57                         cpu_wait();
  58 }
  59
  60 static void ar71xx_halt(void)
  61 {
  62         while (1)
  63                 cpu_wait();
  64 }
  65
  66 static void __init ar71xx_detect_mem_size(void)
  67 {
  68         unsigned long size;
  69
  70         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  71              size <<= 1) {
  72                 if (!memcmp(ar71xx_detect_mem_size,
  73                             ar71xx_detect_mem_size + size, 1024))
  74                         break;
  75         }
  76
  77         add_memory_region(0, size, BOOT_MEM_RAM);
  78 }
  79
  80 static void __init ar71xx_detect_sys_type(void)
  81 {
  82         char *chip = "????";
  83         u32 id;
  84         u32 major;
  85         u32 minor;
  86         u32 rev = 0;
  87
  88         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
  89         major = id & REV_ID_MAJOR_MASK;
  90
  91         switch (major) {
  92         case REV_ID_MAJOR_AR71XX:
  93                 minor = id & AR71XX_REV_ID_MINOR_MASK;
  94                 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
  95                 rev &= AR71XX_REV_ID_REVISION_MASK;
  96                 switch (minor) {
  97                 case AR71XX_REV_ID_MINOR_AR7130:
  98                         ar71xx_soc = AR71XX_SOC_AR7130;
  99                         chip = "7130";
 100                         break;
 101
 102                 case AR71XX_REV_ID_MINOR_AR7141:
 103                         ar71xx_soc = AR71XX_SOC_AR7141;
 104                         chip = "7141";
 105                         break;
 106
 107                 case AR71XX_REV_ID_MINOR_AR7161:
 108                         ar71xx_soc = AR71XX_SOC_AR7161;
 109                         chip = "7161";
 110                         break;
 111                 }
 112                 break;
 113
 114         case REV_ID_MAJOR_AR7240:
 115                 ar71xx_soc = AR71XX_SOC_AR7240;
 116                 chip = "7240";
 117                 rev = (id & AR724X_REV_ID_REVISION_MASK);
 118                 break;
 119
 120         case REV_ID_MAJOR_AR7241:
 121                 ar71xx_soc = AR71XX_SOC_AR7241;
 122                 chip = "7241";
 123                 rev = (id & AR724X_REV_ID_REVISION_MASK);
 124                 break;
 125
 126         case REV_ID_MAJOR_AR7242:
 127                 ar71xx_soc = AR71XX_SOC_AR7242;
 128                 chip = "7242";
 129                 rev = (id & AR724X_REV_ID_REVISION_MASK);
 130                 break;
 131
 132         case REV_ID_MAJOR_AR913X:
 133                 minor = id & AR91XX_REV_ID_MINOR_MASK;
 134                 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
 135                 rev &= AR91XX_REV_ID_REVISION_MASK;
 136                 switch (minor) {
 137                 case AR91XX_REV_ID_MINOR_AR9130:
 138                         ar71xx_soc = AR71XX_SOC_AR9130;
 139                         chip = "9130";
 140                         break;
 141
 142                 case AR91XX_REV_ID_MINOR_AR9132:
 143                         ar71xx_soc = AR71XX_SOC_AR9132;
 144                         chip = "9132";
 145                         break;
 146                 }
 147                 break;
 148
 149         case REV_ID_MAJOR_AR9341:
 150                 ar71xx_soc = AR71XX_SOC_AR9341;
 151                 chip = "9341";
 152                 rev = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) &
 153                         AR934X_REV_ID_REVISION_MASK;
 154                 break;
 155
 156         case REV_ID_MAJOR_AR9342:
 157                 ar71xx_soc = AR71XX_SOC_AR9342;
 158                 chip = "9342";
 159                 rev = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) &
 160                         AR934X_REV_ID_REVISION_MASK;
 161                 break;
 162
 163         case REV_ID_MAJOR_AR9344:
 164                 ar71xx_soc = AR71XX_SOC_AR9344;
 165                 chip = "9344";
 166                 rev = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) &
 167                         AR934X_REV_ID_REVISION_MASK;
 168                 break;
 169
 170         default:
 171                 panic("ar71xx: unknown chip id:0x%08x\n", id);
 172         }
 173
 174         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
 175 }
 176
 177 static void __init ar934x_detect_sys_frequency(void)
 178 {
 179         u32 pll, out_div, ref_div, nint, frac, clk_ctrl, ref, postdiv;
 180
 181         if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40)
 182                 ref = (40 * 1000000);
 183         else
 184                 ref = (25 * 1000000);
 185
 186         ar934x_ref_freq = ref;
 187
 188         clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
 189
 190         pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
 191         out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
 192         ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
 193         nint    = AR934X_CPU_PLL_CFG_NINT_GET(pll);
 194         frac    = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);
 195         postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
 196         ar71xx_cpu_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1);
 197
 198         out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
 199         ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
 200         nint    = AR934X_DDR_PLL_CFG_NINT_GET(pll);
 201         frac    = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);
 202         postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
 203         ar71xx_ddr_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1);
 204
 205         postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
 206
 207         if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) {
 208                 ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1);
 209         } else {
 210                 ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1);
 211         }
 212
 213 }
 214
 215 static void __init ar91xx_detect_sys_frequency(void)
 216 {
 217         u32 pll;
 218         u32 freq;
 219         u32 div;
 220
 221         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 222
 223         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 224         freq = div * AR91XX_BASE_FREQ;
 225
 226         ar71xx_cpu_freq = freq;
 227
 228         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 229         ar71xx_ddr_freq = freq / div;
 230
 231         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 232         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 233 }
 234
 235 static void __init ar71xx_detect_sys_frequency(void)
 236 {
 237         u32 pll;
 238         u32 freq;
 239         u32 div;
 240
 241         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 242
 243         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 244         freq = div * AR71XX_BASE_FREQ;
 245
 246         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 247         ar71xx_cpu_freq = freq / div;
 248
 249         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 250         ar71xx_ddr_freq = freq / div;
 251
 252         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 253         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 254 }
 255
 256 static void __init ar724x_detect_sys_frequency(void)
 257 {
 258         u32 pll;
 259         u32 freq;
 260         u32 div;
 261
 262         pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 263
 264         div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
 265         freq = div * AR724X_BASE_FREQ;
 266
 267         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
 268         freq *= div;
 269
 270         ar71xx_cpu_freq = freq;
 271
 272         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 273         ar71xx_ddr_freq = freq / div;
 274
 275         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 276         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 277 }
 278
 279 static void __init detect_sys_frequency(void)
 280 {
 281         switch (ar71xx_soc) {
 282         case AR71XX_SOC_AR7130:
 283         case AR71XX_SOC_AR7141:
 284         case AR71XX_SOC_AR7161:
 285                 ar71xx_detect_sys_frequency();
 286                 break;
 287
 288         case AR71XX_SOC_AR7240:
 289         case AR71XX_SOC_AR7241:
 290         case AR71XX_SOC_AR7242:
 291                 ar724x_detect_sys_frequency();
 292                 break;
 293
 294         case AR71XX_SOC_AR9130:
 295         case AR71XX_SOC_AR9132:
 296                 ar91xx_detect_sys_frequency();
 297                 break;
 298
 299         case AR71XX_SOC_AR9341:
 300         case AR71XX_SOC_AR9342:
 301         case AR71XX_SOC_AR9344:
 302                 ar934x_detect_sys_frequency();
 303                 break;
 304         default:
 305                 BUG();
 306         }
 307 }
 308
 309 const char *get_system_type(void)
 310 {
 311         return ar71xx_sys_type;
 312 }
 313
 314 unsigned int __cpuinit get_c0_compare_irq(void)
 315 {
 316         return CP0_LEGACY_COMPARE_IRQ;
 317 }
 318
 319 void __init plat_mem_setup(void)
 320 {
 321         set_io_port_base(KSEG1);
 322
 323         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 324                                                 AR71XX_DDR_CTRL_SIZE);
 325
 326         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 327                                                 AR71XX_PLL_SIZE);
 328
 329         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 330                                                 AR71XX_RESET_SIZE);
 331
 332         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 333
 334         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 335                                                 AR71XX_USB_CTRL_SIZE);
 336
 337         ar71xx_detect_mem_size();
 338         ar71xx_detect_sys_type();
 339         detect_sys_frequency();
 340
 341         printk(KERN_INFO
 342                 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
 343                 ar71xx_sys_type,
 344                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 345                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 346                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
 347
 348         _machine_restart = ar71xx_restart;
 349         _machine_halt = ar71xx_halt;
 350         pm_power_off = ar71xx_halt;
 351 }
 352
 353 void __init plat_time_init(void)
 354 {
 355         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 356 }
 357
 358 __setup("board=", mips_machtype_setup);
 359
 360 static int __init ar71xx_machine_setup(void)
 361 {
 362         ar71xx_gpio_init();
 363
 364         ar71xx_add_device_uart();
 365         ar71xx_add_device_wdt();
 366
 367         mips_machine_setup();
 368         return 0;
 369 }
 370
 371 arch_initcall(ar71xx_machine_setup);
 372
 373 static void __init ar71xx_generic_init(void)
 374 {
 375         /* Nothing to do */
 376 }
 377
 378 MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board",
 379              ar71xx_generic_init);