target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/bootmem.h>
  17
  18 #include <asm/bootinfo.h>
  19 #include <asm/time.h>           /* for mips_hpt_frequency */
  20 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  21 #include <asm/mips_machine.h>
  22
  23 #include <asm/mach-ar71xx/ar71xx.h>
  24
  25 #include "machtype.h"
  26 #include "devices.h"
  27
  28 #define AR71XX_SYS_TYPE_LEN     64
  29 #define AR71XX_BASE_FREQ        40000000
  30 #define AR91XX_BASE_FREQ        5000000
  31 #define AR724X_BASE_FREQ        5000000
  32
  33 u32 ar71xx_cpu_freq;
  34 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  35
  36 u32 ar71xx_ahb_freq;
  37 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  38
  39 u32 ar71xx_ddr_freq;
  40 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  41
  42 enum ar71xx_soc_type ar71xx_soc;
  43 EXPORT_SYMBOL_GPL(ar71xx_soc);
  44
  45 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  46
  47 static void ar71xx_restart(char *command)
  48 {
  49         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  50         for (;;)
  51                 if (cpu_wait)
  52                         cpu_wait();
  53 }
  54
  55 static void ar71xx_halt(void)
  56 {
  57         while (1)
  58                 cpu_wait();
  59 }
  60
  61 static void __init ar71xx_detect_mem_size(void)
  62 {
  63         unsigned long size;
  64
  65         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  66              size <<= 1) {
  67                 if (!memcmp(ar71xx_detect_mem_size,
  68                             ar71xx_detect_mem_size + size, 1024))
  69                         break;
  70         }
  71
  72         add_memory_region(0, size, BOOT_MEM_RAM);
  73 }
  74
  75 static void __init ar71xx_detect_sys_type(void)
  76 {
  77         char *chip = "????";
  78         u32 id;
  79         u32 major;
  80         u32 minor;
  81         u32 rev = 0;
  82
  83         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
  84         major = id & REV_ID_MAJOR_MASK;
  85
  86         switch (major) {
  87         case REV_ID_MAJOR_AR71XX:
  88                 minor = id & AR71XX_REV_ID_MINOR_MASK;
  89                 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
  90                 rev &= AR71XX_REV_ID_REVISION_MASK;
  91                 switch (minor) {
  92                 case AR71XX_REV_ID_MINOR_AR7130:
  93                         ar71xx_soc = AR71XX_SOC_AR7130;
  94                         chip = "7130";
  95                         break;
  96
  97                 case AR71XX_REV_ID_MINOR_AR7141:
  98                         ar71xx_soc = AR71XX_SOC_AR7141;
  99                         chip = "7141";
 100                         break;
 101
 102                 case AR71XX_REV_ID_MINOR_AR7161:
 103                         ar71xx_soc = AR71XX_SOC_AR7161;
 104                         chip = "7161";
 105                         break;
 106                 }
 107                 break;
 108
 109         case REV_ID_MAJOR_AR7240:
 110                 ar71xx_soc = AR71XX_SOC_AR7240;
 111                 chip = "7240";
 112                 rev = (id & AR724X_REV_ID_REVISION_MASK);
 113                 break;
 114
 115         case REV_ID_MAJOR_AR7241:
 116                 ar71xx_soc = AR71XX_SOC_AR7241;
 117                 chip = "7241";
 118                 rev = (id & AR724X_REV_ID_REVISION_MASK);
 119                 break;
 120
 121         case REV_ID_MAJOR_AR7242:
 122                 ar71xx_soc = AR71XX_SOC_AR7242;
 123                 chip = "7242";
 124                 rev = (id & AR724X_REV_ID_REVISION_MASK);
 125                 break;
 126
 127         case REV_ID_MAJOR_AR913X:
 128                 minor = id & AR91XX_REV_ID_MINOR_MASK;
 129                 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
 130                 rev &= AR91XX_REV_ID_REVISION_MASK;
 131                 switch (minor) {
 132                 case AR91XX_REV_ID_MINOR_AR9130:
 133                         ar71xx_soc = AR71XX_SOC_AR9130;
 134                         chip = "9130";
 135                         break;
 136
 137                 case AR91XX_REV_ID_MINOR_AR9132:
 138                         ar71xx_soc = AR71XX_SOC_AR9132;
 139                         chip = "9132";
 140                         break;
 141                 }
 142                 break;
 143
 144         default:
 145                 panic("ar71xx: unknown chip id:0x%08x\n", id);
 146         }
 147
 148         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
 149 }
 150
 151 static void __init ar91xx_detect_sys_frequency(void)
 152 {
 153         u32 pll;
 154         u32 freq;
 155         u32 div;
 156
 157         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 158
 159         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 160         freq = div * AR91XX_BASE_FREQ;
 161
 162         ar71xx_cpu_freq = freq;
 163
 164         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 165         ar71xx_ddr_freq = freq / div;
 166
 167         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 168         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 169 }
 170
 171 static void __init ar71xx_detect_sys_frequency(void)
 172 {
 173         u32 pll;
 174         u32 freq;
 175         u32 div;
 176
 177         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 178
 179         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 180         freq = div * AR71XX_BASE_FREQ;
 181
 182         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 183         ar71xx_cpu_freq = freq / div;
 184
 185         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 186         ar71xx_ddr_freq = freq / div;
 187
 188         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 189         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 190 }
 191
 192 static void __init ar724x_detect_sys_frequency(void)
 193 {
 194         u32 pll;
 195         u32 freq;
 196         u32 div;
 197
 198         pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 199
 200         div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
 201         freq = div * AR724X_BASE_FREQ;
 202
 203         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
 204         freq *= div;
 205
 206         ar71xx_cpu_freq = freq;
 207
 208         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 209         ar71xx_ddr_freq = freq / div;
 210
 211         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 212         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 213 }
 214
 215 static void __init detect_sys_frequency(void)
 216 {
 217         switch (ar71xx_soc) {
 218         case AR71XX_SOC_AR7130:
 219         case AR71XX_SOC_AR7141:
 220         case AR71XX_SOC_AR7161:
 221                 ar71xx_detect_sys_frequency();
 222                 break;
 223
 224         case AR71XX_SOC_AR7240:
 225         case AR71XX_SOC_AR7241:
 226         case AR71XX_SOC_AR7242:
 227                 ar724x_detect_sys_frequency();
 228                 break;
 229
 230         case AR71XX_SOC_AR9130:
 231         case AR71XX_SOC_AR9132:
 232                 ar91xx_detect_sys_frequency();
 233                 break;
 234
 235         default:
 236                 BUG();
 237         }
 238 }
 239
 240 const char *get_system_type(void)
 241 {
 242         return ar71xx_sys_type;
 243 }
 244
 245 unsigned int __cpuinit get_c0_compare_irq(void)
 246 {
 247         return CP0_LEGACY_COMPARE_IRQ;
 248 }
 249
 250 void __init plat_mem_setup(void)
 251 {
 252         set_io_port_base(KSEG1);
 253
 254         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 255                                                 AR71XX_DDR_CTRL_SIZE);
 256
 257         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 258                                                 AR71XX_PLL_SIZE);
 259
 260         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 261                                                 AR71XX_RESET_SIZE);
 262
 263         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 264
 265         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 266                                                 AR71XX_USB_CTRL_SIZE);
 267
 268         ar71xx_detect_mem_size();
 269         ar71xx_detect_sys_type();
 270         detect_sys_frequency();
 271
 272         printk(KERN_INFO
 273                 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
 274                 ar71xx_sys_type,
 275                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 276                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 277                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
 278
 279         _machine_restart = ar71xx_restart;
 280         _machine_halt = ar71xx_halt;
 281         pm_power_off = ar71xx_halt;
 282 }
 283
 284 void __init plat_time_init(void)
 285 {
 286         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 287 }
 288
 289 __setup("board=", mips_machtype_setup);
 290
 291 static int __init ar71xx_machine_setup(void)
 292 {
 293         ar71xx_gpio_init();
 294
 295         ar71xx_add_device_uart();
 296         ar71xx_add_device_wdt();
 297
 298         mips_machine_setup();
 299         return 0;
 300 }
 301
 302 arch_initcall(ar71xx_machine_setup);
 303
 304 static void __init ar71xx_generic_init(void)
 305 {
 306         /* Nothing to do */
 307 }
 308
 309 MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board",
 310              ar71xx_generic_init);