target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/bootmem.h>
  21
  22 #include <asm/bootinfo.h>
  23 #include <asm/traps.h>
  24 #include <asm/time.h>           /* for mips_hpt_frequency */
  25 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  26
  27 #include <asm/mach-ar71xx/ar71xx.h>
  28 #include <asm/mach-ar71xx/pci.h>
  29 #include <asm/mach-ar71xx/platform.h>
  30
  31 #define AR71XX_SYS_TYPE_LEN     64
  32 #define AR71XX_BASE_FREQ        40000000
  33 #define AR91XX_BASE_FREQ        5000000
  34
  35 #define AR71XX_MEM_SIZE_MIN     0x0200000
  36 #define AR71XX_MEM_SIZE_MAX     0x8000000
  37
  38 u32 ar71xx_cpu_freq;
  39 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  40
  41 u32 ar71xx_ahb_freq;
  42 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  43
  44 u32 ar71xx_ddr_freq;
  45 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  46
  47 int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
  48                              struct ar71xx_pci_irq *map) __initdata;
  49
  50 int (*ar71xx_pci_be_handler)(int is_fixup);
  51
  52 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  53
  54 static void ar71xx_restart(char *command)
  55 {
  56         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  57         for (;;)
  58                 if (cpu_wait)
  59                         cpu_wait();
  60 }
  61
  62 static void ar71xx_halt(void)
  63 {
  64         while (1)
  65                 cpu_wait();
  66 }
  67
  68 static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup)
  69 {
  70         int err = 0;
  71
  72         if (ar71xx_pci_be_handler)
  73                 err = ar71xx_pci_be_handler(is_fixup);
  74
  75         return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
  76 }
  77
  78 int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
  79 {
  80         if (!ar71xx_pci_bios_init)
  81                 return 0;
  82
  83         return ar71xx_pci_bios_init(nr_irqs, map);
  84 }
  85
  86 static void __init ar71xx_detect_mem_size(void)
  87 {
  88         volatile u8 *p;
  89         u8 memsave;
  90         u32 size;
  91
  92         p = (volatile u8 *) KSEG1ADDR(0);
  93         memsave = *p;
  94         for (size = AR71XX_MEM_SIZE_MIN;
  95              size <= (AR71XX_MEM_SIZE_MAX >> 1); size <<= 1) {
  96                 volatile u8 *r;
  97
  98                 r = (p + size);
  99                 *p = 0x55;
 100                 if (*r == 0x55) {
 101                         /* Mirrored data found, try another pattern */
 102                         *p = 0xAA;
 103                         if (*r == 0xAA) {
 104                                 /* Mirrored data found again, stop detection */
 105                                 break;
 106                         }
 107                 }
 108         }
 109         *p = memsave;
 110
 111         add_memory_region(0, size, BOOT_MEM_RAM);
 112 }
 113
 114 static void __init ar71xx_detect_sys_type(void)
 115 {
 116         char *chip;
 117         u32 id;
 118         u32 rev;
 119
 120         id = ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK;
 121         rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
 122         switch (id & REV_ID_CHIP_MASK) {
 123         case REV_ID_CHIP_AR7130:
 124                 chip = "7130";
 125                 break;
 126         case REV_ID_CHIP_AR7141:
 127                 chip = "7141";
 128                 break;
 129         case REV_ID_CHIP_AR7161:
 130                 chip = "7161";
 131                 break;
 132         case REV_ID_CHIP_AR9130:
 133                 chip = "9130";
 134                 break;
 135         default:
 136                 chip = "71xx";
 137         }
 138
 139         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u (id:0x%02x)",
 140                 chip, rev, id);
 141 }
 142
 143 static void __init ar91xx_detect_sys_frequency(void)
 144 {
 145         u32 pll;
 146         u32 freq;
 147         u32 div;
 148
 149         pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
 150
 151         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 152         freq = div * AR91XX_BASE_FREQ;
 153
 154         ar71xx_cpu_freq = freq;
 155
 156         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 157         ar71xx_ddr_freq = freq / div;
 158
 159         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 160         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 161 }
 162
 163 static void __init ar71xx_detect_sys_frequency(void)
 164 {
 165         u32 pll;
 166         u32 freq;
 167         u32 div;
 168
 169         if ((ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK) >=
 170                         REV_ID_CHIP_AR9130) {
 171                 return ar91xx_detect_sys_frequency();
 172         }
 173
 174         pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
 175
 176         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 177         freq = div * AR71XX_BASE_FREQ;
 178
 179         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 180         ar71xx_cpu_freq = freq / div;
 181
 182         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 183         ar71xx_ddr_freq = freq / div;
 184
 185         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 186         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 187 }
 188
 189 #ifdef CONFIG_AR71XX_EARLY_SERIAL
 190 static void __init ar71xx_early_serial_setup(void)
 191 {
 192         struct uart_port p;
 193
 194         memset(&p, 0, sizeof(p));
 195
 196         p.flags         = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
 197         p.iotype        = UPIO_MEM32;
 198         p.uartclk       = ar71xx_ahb_freq;
 199         p.irq           = AR71XX_MISC_IRQ_UART;
 200         p.regshift      = 2;
 201         p.mapbase       = AR71XX_UART_BASE;
 202
 203         early_serial_setup(&p);
 204 }
 205 #else
 206 static inline void ar71xx_early_serial_setup(void) {};
 207 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
 208
 209 const char *get_system_type(void)
 210 {
 211         return ar71xx_sys_type;
 212 }
 213
 214 unsigned int __cpuinit get_c0_compare_irq(void)
 215 {
 216         return CP0_LEGACY_COMPARE_IRQ;
 217 }
 218
 219 void __init plat_mem_setup(void)
 220 {
 221         set_io_port_base(KSEG1);
 222
 223         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 224                                                 AR71XX_DDR_CTRL_SIZE);
 225
 226         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 227                                                 AR71XX_PLL_SIZE);
 228
 229         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 230                                                 AR71XX_RESET_SIZE);
 231
 232         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 233
 234         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 235                                                 AR71XX_USB_CTRL_SIZE);
 236
 237         ar71xx_detect_mem_size();
 238         ar71xx_detect_sys_type();
 239         ar71xx_detect_sys_frequency();
 240
 241         _machine_restart = ar71xx_restart;
 242         _machine_halt = ar71xx_halt;
 243         pm_power_off = ar71xx_halt;
 244
 245         board_be_handler = ar71xx_be_handler;
 246
 247         ar71xx_early_serial_setup();
 248 }
 249
 250 void __init plat_time_init(void)
 251 {
 252         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 253 }