[ar71xx] rewrite memory size detection
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ar71xx / setup.c
1 /*
2 * Atheros AR71xx SoC specific setup
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/pci.h>
19 #include <linux/serial_8250.h>
20 #include <linux/bootmem.h>
21
22 #include <asm/bootinfo.h>
23 #include <asm/traps.h>
24 #include <asm/time.h> /* for mips_hpt_frequency */
25 #include <asm/reboot.h> /* for _machine_{restart,halt} */
26
27 #include <asm/mach-ar71xx/ar71xx.h>
28 #include <asm/mach-ar71xx/pci.h>
29 #include <asm/mach-ar71xx/platform.h>
30
31 #define AR71XX_SYS_TYPE_LEN 64
32 #define AR71XX_BASE_FREQ 40000000
33 #define AR91XX_BASE_FREQ 5000000
34
35 #define AR71XX_MEM_SIZE_MIN 0x0200000
36 #define AR71XX_MEM_SIZE_MAX 0x8000000
37
38 u32 ar71xx_cpu_freq;
39 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
40
41 u32 ar71xx_ahb_freq;
42 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
43
44 u32 ar71xx_ddr_freq;
45 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
46
47 int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
48 struct ar71xx_pci_irq *map) __initdata;
49
50 int (*ar71xx_pci_be_handler)(int is_fixup);
51
52 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
53
54 static void ar71xx_restart(char *command)
55 {
56 ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
57 for (;;)
58 if (cpu_wait)
59 cpu_wait();
60 }
61
62 static void ar71xx_halt(void)
63 {
64 while (1)
65 cpu_wait();
66 }
67
68 static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup)
69 {
70 int err = 0;
71
72 if (ar71xx_pci_be_handler)
73 err = ar71xx_pci_be_handler(is_fixup);
74
75 return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
76 }
77
78 int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
79 {
80 if (!ar71xx_pci_bios_init)
81 return 0;
82
83 return ar71xx_pci_bios_init(nr_irqs, map);
84 }
85
86 static void __init ar71xx_detect_mem_size(void)
87 {
88 unsigned long size;
89
90 for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
91 size <<= 1 ) {
92 if (!memcmp(ar71xx_detect_mem_size,
93 ar71xx_detect_mem_size + size, 1024))
94 break;
95 }
96
97 add_memory_region(0, size, BOOT_MEM_RAM);
98 }
99
100 static void __init ar71xx_detect_sys_type(void)
101 {
102 char *chip;
103 u32 id;
104 u32 rev;
105
106 id = ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK;
107 rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
108 switch (id & REV_ID_CHIP_MASK) {
109 case REV_ID_CHIP_AR7130:
110 chip = "7130";
111 break;
112 case REV_ID_CHIP_AR7141:
113 chip = "7141";
114 break;
115 case REV_ID_CHIP_AR7161:
116 chip = "7161";
117 break;
118 case REV_ID_CHIP_AR9130:
119 chip = "9130";
120 break;
121 default:
122 chip = "71xx";
123 }
124
125 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u (id:0x%02x)",
126 chip, rev, id);
127 }
128
129 static void __init ar91xx_detect_sys_frequency(void)
130 {
131 u32 pll;
132 u32 freq;
133 u32 div;
134
135 pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
136
137 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
138 freq = div * AR91XX_BASE_FREQ;
139
140 ar71xx_cpu_freq = freq;
141
142 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
143 ar71xx_ddr_freq = freq / div;
144
145 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
146 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
147 }
148
149 static void __init ar71xx_detect_sys_frequency(void)
150 {
151 u32 pll;
152 u32 freq;
153 u32 div;
154
155 if ((ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK) >=
156 REV_ID_CHIP_AR9130) {
157 return ar91xx_detect_sys_frequency();
158 }
159
160 pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
161
162 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
163 freq = div * AR71XX_BASE_FREQ;
164
165 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
166 ar71xx_cpu_freq = freq / div;
167
168 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
169 ar71xx_ddr_freq = freq / div;
170
171 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
172 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
173 }
174
175 #ifdef CONFIG_AR71XX_EARLY_SERIAL
176 static void __init ar71xx_early_serial_setup(void)
177 {
178 struct uart_port p;
179
180 memset(&p, 0, sizeof(p));
181
182 p.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
183 p.iotype = UPIO_MEM32;
184 p.uartclk = ar71xx_ahb_freq;
185 p.irq = AR71XX_MISC_IRQ_UART;
186 p.regshift = 2;
187 p.mapbase = AR71XX_UART_BASE;
188
189 early_serial_setup(&p);
190 }
191 #else
192 static inline void ar71xx_early_serial_setup(void) {};
193 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
194
195 const char *get_system_type(void)
196 {
197 return ar71xx_sys_type;
198 }
199
200 unsigned int __cpuinit get_c0_compare_irq(void)
201 {
202 return CP0_LEGACY_COMPARE_IRQ;
203 }
204
205 void __init plat_mem_setup(void)
206 {
207 set_io_port_base(KSEG1);
208
209 ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
210 AR71XX_DDR_CTRL_SIZE);
211
212 ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
213 AR71XX_PLL_SIZE);
214
215 ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
216 AR71XX_RESET_SIZE);
217
218 ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
219
220 ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
221 AR71XX_USB_CTRL_SIZE);
222
223 ar71xx_detect_mem_size();
224 ar71xx_detect_sys_type();
225 ar71xx_detect_sys_frequency();
226
227 _machine_restart = ar71xx_restart;
228 _machine_halt = ar71xx_halt;
229 pm_power_off = ar71xx_halt;
230
231 board_be_handler = ar71xx_be_handler;
232
233 ar71xx_early_serial_setup();
234 }
235
236 void __init plat_time_init(void)
237 {
238 mips_hpt_frequency = ar71xx_cpu_freq / 2;
239 }