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ar71xx: reset the switch on AR934x before ethernet device registration
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/irq.h>
26
27 #include "common.h"
28 #include "dev-eth.h"
29
30 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
31
32 static struct resource ath79_mdio0_resources[] = {
33 {
34 .name = "mdio_base",
35 .flags = IORESOURCE_MEM,
36 .start = AR71XX_GE0_BASE,
37 .end = AR71XX_GE0_BASE + 0x200 - 1,
38 }
39 };
40
41 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
42
43 struct platform_device ath79_mdio0_device = {
44 .name = "ag71xx-mdio",
45 .id = 0,
46 .resource = ath79_mdio0_resources,
47 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
48 .dev = {
49 .platform_data = &ath79_mdio0_data,
50 },
51 };
52
53 static struct resource ath79_mdio1_resources[] = {
54 {
55 .name = "mdio_base",
56 .flags = IORESOURCE_MEM,
57 .start = AR71XX_GE1_BASE,
58 .end = AR71XX_GE1_BASE + 0x200 - 1,
59 }
60 };
61
62 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
63
64 struct platform_device ath79_mdio1_device = {
65 .name = "ag71xx-mdio",
66 .id = 1,
67 .resource = ath79_mdio1_resources,
68 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
69 .dev = {
70 .platform_data = &ath79_mdio1_data,
71 },
72 };
73
74 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
75 {
76 void __iomem *base;
77 u32 t;
78
79 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
80
81 t = __raw_readl(base + cfg_reg);
82 t &= ~(3 << shift);
83 t |= (2 << shift);
84 __raw_writel(t, base + cfg_reg);
85 udelay(100);
86
87 __raw_writel(pll_val, base + pll_reg);
88
89 t |= (3 << shift);
90 __raw_writel(t, base + cfg_reg);
91 udelay(100);
92
93 t &= ~(3 << shift);
94 __raw_writel(t, base + cfg_reg);
95 udelay(100);
96
97 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
98 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
99
100 iounmap(base);
101 }
102
103 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
104 unsigned int mii_if)
105 {
106 void __iomem *base;
107 u32 t;
108
109 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
110
111 t = __raw_readl(base + reg);
112 t &= ~(AR71XX_MII_CTRL_IF_MASK);
113 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
114 __raw_writel(t, base + reg);
115
116 iounmap(base);
117 }
118
119 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
120 {
121 void __iomem *base;
122 unsigned int mii_speed;
123 u32 t;
124
125 switch (speed) {
126 case SPEED_10:
127 mii_speed = AR71XX_MII_CTRL_SPEED_10;
128 break;
129 case SPEED_100:
130 mii_speed = AR71XX_MII_CTRL_SPEED_100;
131 break;
132 case SPEED_1000:
133 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
134 break;
135 default:
136 BUG();
137 }
138
139 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
140
141 t = __raw_readl(base + reg);
142 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
143 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
144 __raw_writel(t, base + reg);
145
146 iounmap(base);
147 }
148
149 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
150 {
151 struct platform_device *mdio_dev;
152 struct ag71xx_mdio_platform_data *mdio_data;
153 unsigned int max_id;
154
155 if (ath79_soc == ATH79_SOC_AR9341 ||
156 ath79_soc == ATH79_SOC_AR9342 ||
157 ath79_soc == ATH79_SOC_AR9344)
158 max_id = 1;
159 else
160 max_id = 0;
161
162 if (id > max_id) {
163 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
164 return;
165 }
166
167 switch (ath79_soc) {
168 case ATH79_SOC_AR7241:
169 case ATH79_SOC_AR9330:
170 case ATH79_SOC_AR9331:
171 mdio_dev = &ath79_mdio1_device;
172 mdio_data = &ath79_mdio1_data;
173 break;
174
175 case ATH79_SOC_AR9341:
176 case ATH79_SOC_AR9342:
177 case ATH79_SOC_AR9344:
178 if (id == 0) {
179 mdio_dev = &ath79_mdio0_device;
180 mdio_data = &ath79_mdio0_data;
181 } else {
182 mdio_dev = &ath79_mdio1_device;
183 mdio_data = &ath79_mdio1_data;
184 }
185 break;
186
187 case ATH79_SOC_AR7242:
188 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
189 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
190 AR71XX_ETH0_PLL_SHIFT);
191 /* fall through */
192 default:
193 mdio_dev = &ath79_mdio0_device;
194 mdio_data = &ath79_mdio0_data;
195 break;
196 }
197
198 mdio_data->phy_mask = phy_mask;
199
200 switch (ath79_soc) {
201 case ATH79_SOC_AR7240:
202 case ATH79_SOC_AR7241:
203 case ATH79_SOC_AR9330:
204 case ATH79_SOC_AR9331:
205 mdio_data->is_ar7240 = 1;
206 break;
207
208 case ATH79_SOC_AR9341:
209 case ATH79_SOC_AR9342:
210 case ATH79_SOC_AR9344:
211 if (id == 1)
212 mdio_data->is_ar7240 = 1;
213 break;
214
215 default:
216 break;
217 }
218
219 platform_device_register(mdio_dev);
220 }
221
222 struct ath79_eth_pll_data ath79_eth0_pll_data;
223 struct ath79_eth_pll_data ath79_eth1_pll_data;
224
225 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
226 {
227 struct ath79_eth_pll_data *pll_data;
228 u32 pll_val;
229
230 switch (mac) {
231 case 0:
232 pll_data = &ath79_eth0_pll_data;
233 break;
234 case 1:
235 pll_data = &ath79_eth1_pll_data;
236 break;
237 default:
238 BUG();
239 }
240
241 switch (speed) {
242 case SPEED_10:
243 pll_val = pll_data->pll_10;
244 break;
245 case SPEED_100:
246 pll_val = pll_data->pll_100;
247 break;
248 case SPEED_1000:
249 pll_val = pll_data->pll_1000;
250 break;
251 default:
252 BUG();
253 }
254
255 return pll_val;
256 }
257
258 static void ath79_set_speed_ge0(int speed)
259 {
260 u32 val = ath79_get_eth_pll(0, speed);
261
262 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
263 val, AR71XX_ETH0_PLL_SHIFT);
264 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
265 }
266
267 static void ath79_set_speed_ge1(int speed)
268 {
269 u32 val = ath79_get_eth_pll(1, speed);
270
271 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
272 val, AR71XX_ETH1_PLL_SHIFT);
273 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
274 }
275
276 static void ar7242_set_speed_ge0(int speed)
277 {
278 u32 val = ath79_get_eth_pll(0, speed);
279 void __iomem *base;
280
281 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
282 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
283 iounmap(base);
284 }
285
286 static void ar91xx_set_speed_ge0(int speed)
287 {
288 u32 val = ath79_get_eth_pll(0, speed);
289
290 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
291 val, AR913X_ETH0_PLL_SHIFT);
292 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
293 }
294
295 static void ar91xx_set_speed_ge1(int speed)
296 {
297 u32 val = ath79_get_eth_pll(1, speed);
298
299 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
300 val, AR913X_ETH1_PLL_SHIFT);
301 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
302 }
303
304 static void ar934x_set_speed_ge0(int speed)
305 {
306 /* TODO */
307 }
308
309 static void ath79_set_speed_dummy(int speed)
310 {
311 }
312
313 static void ath79_ddr_no_flush(void)
314 {
315 }
316
317 static void ath79_ddr_flush_ge0(void)
318 {
319 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
320 }
321
322 static void ath79_ddr_flush_ge1(void)
323 {
324 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
325 }
326
327 static void ar724x_ddr_flush_ge0(void)
328 {
329 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
330 }
331
332 static void ar724x_ddr_flush_ge1(void)
333 {
334 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
335 }
336
337 static void ar91xx_ddr_flush_ge0(void)
338 {
339 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
340 }
341
342 static void ar91xx_ddr_flush_ge1(void)
343 {
344 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
345 }
346
347 static void ar933x_ddr_flush_ge0(void)
348 {
349 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
350 }
351
352 static void ar933x_ddr_flush_ge1(void)
353 {
354 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
355 }
356
357 static struct resource ath79_eth0_resources[] = {
358 {
359 .name = "mac_base",
360 .flags = IORESOURCE_MEM,
361 .start = AR71XX_GE0_BASE,
362 .end = AR71XX_GE0_BASE + 0x200 - 1,
363 }, {
364 .name = "mac_irq",
365 .flags = IORESOURCE_IRQ,
366 .start = ATH79_CPU_IRQ_GE0,
367 .end = ATH79_CPU_IRQ_GE0,
368 },
369 };
370
371 struct ag71xx_platform_data ath79_eth0_data = {
372 .reset_bit = AR71XX_RESET_GE0_MAC,
373 };
374
375 struct platform_device ath79_eth0_device = {
376 .name = "ag71xx",
377 .id = 0,
378 .resource = ath79_eth0_resources,
379 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
380 .dev = {
381 .platform_data = &ath79_eth0_data,
382 },
383 };
384
385 static struct resource ath79_eth1_resources[] = {
386 {
387 .name = "mac_base",
388 .flags = IORESOURCE_MEM,
389 .start = AR71XX_GE1_BASE,
390 .end = AR71XX_GE1_BASE + 0x200 - 1,
391 }, {
392 .name = "mac_irq",
393 .flags = IORESOURCE_IRQ,
394 .start = ATH79_CPU_IRQ_GE1,
395 .end = ATH79_CPU_IRQ_GE1,
396 },
397 };
398
399 struct ag71xx_platform_data ath79_eth1_data = {
400 .reset_bit = AR71XX_RESET_GE1_MAC,
401 };
402
403 struct platform_device ath79_eth1_device = {
404 .name = "ag71xx",
405 .id = 1,
406 .resource = ath79_eth1_resources,
407 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
408 .dev = {
409 .platform_data = &ath79_eth1_data,
410 },
411 };
412
413 struct ag71xx_switch_platform_data ath79_switch_data;
414
415 #define AR71XX_PLL_VAL_1000 0x00110000
416 #define AR71XX_PLL_VAL_100 0x00001099
417 #define AR71XX_PLL_VAL_10 0x00991099
418
419 #define AR724X_PLL_VAL_1000 0x00110000
420 #define AR724X_PLL_VAL_100 0x00001099
421 #define AR724X_PLL_VAL_10 0x00991099
422
423 #define AR7242_PLL_VAL_1000 0x16000000
424 #define AR7242_PLL_VAL_100 0x00000101
425 #define AR7242_PLL_VAL_10 0x00001616
426
427 #define AR913X_PLL_VAL_1000 0x1a000000
428 #define AR913X_PLL_VAL_100 0x13000a44
429 #define AR913X_PLL_VAL_10 0x00441099
430
431 #define AR933X_PLL_VAL_1000 0x00110000
432 #define AR933X_PLL_VAL_100 0x00001099
433 #define AR933X_PLL_VAL_10 0x00991099
434
435 #define AR934X_PLL_VAL_1000 0x00110000
436 #define AR934X_PLL_VAL_100 0x00001099
437 #define AR934X_PLL_VAL_10 0x00991099
438
439 static void __init ath79_init_eth_pll_data(unsigned int id)
440 {
441 struct ath79_eth_pll_data *pll_data;
442 u32 pll_10, pll_100, pll_1000;
443
444 switch (id) {
445 case 0:
446 pll_data = &ath79_eth0_pll_data;
447 break;
448 case 1:
449 pll_data = &ath79_eth1_pll_data;
450 break;
451 default:
452 BUG();
453 }
454
455 switch (ath79_soc) {
456 case ATH79_SOC_AR7130:
457 case ATH79_SOC_AR7141:
458 case ATH79_SOC_AR7161:
459 pll_10 = AR71XX_PLL_VAL_10;
460 pll_100 = AR71XX_PLL_VAL_100;
461 pll_1000 = AR71XX_PLL_VAL_1000;
462 break;
463
464 case ATH79_SOC_AR7240:
465 case ATH79_SOC_AR7241:
466 pll_10 = AR724X_PLL_VAL_10;
467 pll_100 = AR724X_PLL_VAL_100;
468 pll_1000 = AR724X_PLL_VAL_1000;
469 break;
470
471 case ATH79_SOC_AR7242:
472 pll_10 = AR7242_PLL_VAL_10;
473 pll_100 = AR7242_PLL_VAL_100;
474 pll_1000 = AR7242_PLL_VAL_1000;
475 break;
476
477 case ATH79_SOC_AR9130:
478 case ATH79_SOC_AR9132:
479 pll_10 = AR913X_PLL_VAL_10;
480 pll_100 = AR913X_PLL_VAL_100;
481 pll_1000 = AR913X_PLL_VAL_1000;
482 break;
483
484 case ATH79_SOC_AR9330:
485 case ATH79_SOC_AR9331:
486 pll_10 = AR933X_PLL_VAL_10;
487 pll_100 = AR933X_PLL_VAL_100;
488 pll_1000 = AR933X_PLL_VAL_1000;
489 break;
490
491 case ATH79_SOC_AR9341:
492 case ATH79_SOC_AR9342:
493 case ATH79_SOC_AR9344:
494 pll_10 = AR934X_PLL_VAL_10;
495 pll_100 = AR934X_PLL_VAL_100;
496 pll_1000 = AR934X_PLL_VAL_1000;
497 break;
498
499 default:
500 BUG();
501 }
502
503 if (!pll_data->pll_10)
504 pll_data->pll_10 = pll_10;
505
506 if (!pll_data->pll_100)
507 pll_data->pll_100 = pll_100;
508
509 if (!pll_data->pll_1000)
510 pll_data->pll_1000 = pll_1000;
511 }
512
513 static int __init ath79_setup_phy_if_mode(unsigned int id,
514 struct ag71xx_platform_data *pdata)
515 {
516 unsigned int mii_if;
517
518 switch (id) {
519 case 0:
520 switch (ath79_soc) {
521 case ATH79_SOC_AR7130:
522 case ATH79_SOC_AR7141:
523 case ATH79_SOC_AR7161:
524 case ATH79_SOC_AR9130:
525 case ATH79_SOC_AR9132:
526 switch (pdata->phy_if_mode) {
527 case PHY_INTERFACE_MODE_MII:
528 mii_if = AR71XX_MII0_CTRL_IF_MII;
529 break;
530 case PHY_INTERFACE_MODE_GMII:
531 mii_if = AR71XX_MII0_CTRL_IF_GMII;
532 break;
533 case PHY_INTERFACE_MODE_RGMII:
534 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
535 break;
536 case PHY_INTERFACE_MODE_RMII:
537 mii_if = AR71XX_MII0_CTRL_IF_RMII;
538 break;
539 default:
540 return -EINVAL;
541 }
542 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
543 break;
544
545 case ATH79_SOC_AR7240:
546 case ATH79_SOC_AR7241:
547 case ATH79_SOC_AR9330:
548 case ATH79_SOC_AR9331:
549 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
550 break;
551
552 case ATH79_SOC_AR7242:
553 /* FIXME */
554
555 case ATH79_SOC_AR9341:
556 case ATH79_SOC_AR9342:
557 case ATH79_SOC_AR9344:
558 switch (pdata->phy_if_mode) {
559 case PHY_INTERFACE_MODE_MII:
560 case PHY_INTERFACE_MODE_GMII:
561 case PHY_INTERFACE_MODE_RGMII:
562 case PHY_INTERFACE_MODE_RMII:
563 break;
564 default:
565 return -EINVAL;
566 }
567 break;
568
569 default:
570 BUG();
571 }
572 break;
573 case 1:
574 switch (ath79_soc) {
575 case ATH79_SOC_AR7130:
576 case ATH79_SOC_AR7141:
577 case ATH79_SOC_AR7161:
578 case ATH79_SOC_AR9130:
579 case ATH79_SOC_AR9132:
580 switch (pdata->phy_if_mode) {
581 case PHY_INTERFACE_MODE_RMII:
582 mii_if = AR71XX_MII1_CTRL_IF_RMII;
583 break;
584 case PHY_INTERFACE_MODE_RGMII:
585 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
586 break;
587 default:
588 return -EINVAL;
589 }
590 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
591 break;
592
593 case ATH79_SOC_AR7240:
594 case ATH79_SOC_AR7241:
595 case ATH79_SOC_AR9330:
596 case ATH79_SOC_AR9331:
597 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
598 break;
599
600 case ATH79_SOC_AR7242:
601 /* FIXME */
602
603 case ATH79_SOC_AR9341:
604 case ATH79_SOC_AR9342:
605 case ATH79_SOC_AR9344:
606 switch (pdata->phy_if_mode) {
607 case PHY_INTERFACE_MODE_MII:
608 case PHY_INTERFACE_MODE_GMII:
609 break;
610 default:
611 return -EINVAL;
612 }
613 break;
614
615 default:
616 BUG();
617 }
618 break;
619 }
620
621 return 0;
622 }
623
624 static int ath79_eth_instance __initdata;
625 void __init ath79_register_eth(unsigned int id)
626 {
627 struct platform_device *pdev;
628 struct ag71xx_platform_data *pdata;
629 int err;
630
631 if (id > 1) {
632 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
633 return;
634 }
635
636 ath79_init_eth_pll_data(id);
637
638 if (id == 0)
639 pdev = &ath79_eth0_device;
640 else
641 pdev = &ath79_eth1_device;
642
643 pdata = pdev->dev.platform_data;
644
645 err = ath79_setup_phy_if_mode(id, pdata);
646 if (err) {
647 printk(KERN_ERR
648 "ar71xx: invalid PHY interface mode for GE%u\n", id);
649 return;
650 }
651
652 switch (ath79_soc) {
653 case ATH79_SOC_AR7130:
654 if (id == 0) {
655 pdata->ddr_flush = ath79_ddr_flush_ge0;
656 pdata->set_speed = ath79_set_speed_ge0;
657 } else {
658 pdata->ddr_flush = ath79_ddr_flush_ge1;
659 pdata->set_speed = ath79_set_speed_ge1;
660 }
661 break;
662
663 case ATH79_SOC_AR7141:
664 case ATH79_SOC_AR7161:
665 if (id == 0) {
666 pdata->ddr_flush = ath79_ddr_flush_ge0;
667 pdata->set_speed = ath79_set_speed_ge0;
668 } else {
669 pdata->ddr_flush = ath79_ddr_flush_ge1;
670 pdata->set_speed = ath79_set_speed_ge1;
671 }
672 pdata->has_gbit = 1;
673 break;
674
675 case ATH79_SOC_AR7242:
676 if (id == 0) {
677 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
678 AR71XX_RESET_GE0_PHY;
679 pdata->ddr_flush = ar724x_ddr_flush_ge0;
680 pdata->set_speed = ar7242_set_speed_ge0;
681 } else {
682 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
683 AR71XX_RESET_GE1_PHY;
684 pdata->ddr_flush = ar724x_ddr_flush_ge1;
685 pdata->set_speed = ath79_set_speed_dummy;
686 }
687 pdata->has_gbit = 1;
688 pdata->is_ar724x = 1;
689
690 if (!pdata->fifo_cfg1)
691 pdata->fifo_cfg1 = 0x0010ffff;
692 if (!pdata->fifo_cfg2)
693 pdata->fifo_cfg2 = 0x015500aa;
694 if (!pdata->fifo_cfg3)
695 pdata->fifo_cfg3 = 0x01f00140;
696 break;
697
698 case ATH79_SOC_AR7241:
699 if (id == 0)
700 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
701 else
702 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
703 /* fall through */
704 case ATH79_SOC_AR7240:
705 if (id == 0) {
706 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
707 pdata->ddr_flush = ar724x_ddr_flush_ge0;
708 pdata->set_speed = ath79_set_speed_dummy;
709
710 pdata->phy_mask = BIT(4);
711 } else {
712 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
713 pdata->ddr_flush = ar724x_ddr_flush_ge1;
714 pdata->set_speed = ath79_set_speed_dummy;
715
716 pdata->speed = SPEED_1000;
717 pdata->duplex = DUPLEX_FULL;
718 pdata->switch_data = &ath79_switch_data;
719 }
720 pdata->has_gbit = 1;
721 pdata->is_ar724x = 1;
722 if (ath79_soc == ATH79_SOC_AR7240)
723 pdata->is_ar7240 = 1;
724
725 if (!pdata->fifo_cfg1)
726 pdata->fifo_cfg1 = 0x0010ffff;
727 if (!pdata->fifo_cfg2)
728 pdata->fifo_cfg2 = 0x015500aa;
729 if (!pdata->fifo_cfg3)
730 pdata->fifo_cfg3 = 0x01f00140;
731 break;
732
733 case ATH79_SOC_AR9130:
734 if (id == 0) {
735 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
736 pdata->set_speed = ar91xx_set_speed_ge0;
737 } else {
738 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
739 pdata->set_speed = ar91xx_set_speed_ge1;
740 }
741 pdata->is_ar91xx = 1;
742 break;
743
744 case ATH79_SOC_AR9132:
745 if (id == 0) {
746 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
747 pdata->set_speed = ar91xx_set_speed_ge0;
748 } else {
749 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
750 pdata->set_speed = ar91xx_set_speed_ge1;
751 }
752 pdata->is_ar91xx = 1;
753 pdata->has_gbit = 1;
754 break;
755
756 case ATH79_SOC_AR9330:
757 case ATH79_SOC_AR9331:
758 if (id == 0) {
759 pdata->reset_bit = AR933X_RESET_GE0_MAC |
760 AR933X_RESET_GE0_MDIO;
761 pdata->ddr_flush = ar933x_ddr_flush_ge0;
762 pdata->set_speed = ath79_set_speed_dummy;
763
764 pdata->phy_mask = BIT(4);
765 } else {
766 pdata->reset_bit = AR933X_RESET_GE1_MAC |
767 AR933X_RESET_GE1_MDIO;
768 pdata->ddr_flush = ar933x_ddr_flush_ge1;
769 pdata->set_speed = ath79_set_speed_dummy;
770
771 pdata->speed = SPEED_1000;
772 pdata->duplex = DUPLEX_FULL;
773 pdata->switch_data = &ath79_switch_data;
774 }
775
776 pdata->has_gbit = 1;
777 pdata->is_ar724x = 1;
778
779 if (!pdata->fifo_cfg1)
780 pdata->fifo_cfg1 = 0x0010ffff;
781 if (!pdata->fifo_cfg2)
782 pdata->fifo_cfg2 = 0x015500aa;
783 if (!pdata->fifo_cfg3)
784 pdata->fifo_cfg3 = 0x01f00140;
785 break;
786
787 case ATH79_SOC_AR9341:
788 case ATH79_SOC_AR9342:
789 case ATH79_SOC_AR9344:
790 if (id == 0) {
791 pdata->reset_bit = AR934X_RESET_GE0_MAC |
792 AR934X_RESET_GE0_MDIO;
793 pdata->set_speed = ar934x_set_speed_ge0;
794 } else {
795 pdata->reset_bit = AR934X_RESET_GE1_MAC |
796 AR934X_RESET_GE1_MDIO;
797 pdata->set_speed = ath79_set_speed_dummy;
798
799 pdata->switch_data = &ath79_switch_data;
800
801 /* reset the built-in switch */
802 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
803 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
804 }
805
806 pdata->ddr_flush = ath79_ddr_no_flush;
807 pdata->has_gbit = 1;
808 pdata->is_ar724x = 1;
809
810 if (!pdata->fifo_cfg1)
811 pdata->fifo_cfg1 = 0x0010ffff;
812 if (!pdata->fifo_cfg2)
813 pdata->fifo_cfg2 = 0x015500aa;
814 if (!pdata->fifo_cfg3)
815 pdata->fifo_cfg3 = 0x01f00140;
816 break;
817
818 default:
819 BUG();
820 }
821
822 switch (pdata->phy_if_mode) {
823 case PHY_INTERFACE_MODE_GMII:
824 case PHY_INTERFACE_MODE_RGMII:
825 if (!pdata->has_gbit) {
826 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
827 id);
828 return;
829 }
830 /* fallthrough */
831 default:
832 break;
833 }
834
835 if (!is_valid_ether_addr(pdata->mac_addr)) {
836 random_ether_addr(pdata->mac_addr);
837 printk(KERN_DEBUG
838 "ar71xx: using random MAC address for eth%d\n",
839 ath79_eth_instance);
840 }
841
842 if (pdata->mii_bus_dev == NULL) {
843 switch (ath79_soc) {
844 case ATH79_SOC_AR9341:
845 case ATH79_SOC_AR9342:
846 case ATH79_SOC_AR9344:
847 if (id == 0)
848 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
849 else
850 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
851 break;
852
853 case ATH79_SOC_AR7241:
854 case ATH79_SOC_AR9330:
855 case ATH79_SOC_AR9331:
856 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
857 break;
858
859 default:
860 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
861 break;
862 }
863 }
864
865 /* Reset the device */
866 ath79_device_reset_set(pdata->reset_bit);
867 mdelay(100);
868
869 ath79_device_reset_clear(pdata->reset_bit);
870 mdelay(100);
871
872 platform_device_register(pdev);
873 ath79_eth_instance++;
874 }
875
876 void __init ath79_set_mac_base(unsigned char *mac)
877 {
878 memcpy(ath79_mac_base, mac, ETH_ALEN);
879 }
880
881 void __init ath79_parse_mac_addr(char *mac_str)
882 {
883 u8 tmp[ETH_ALEN];
884 int t;
885
886 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
887 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
888
889 if (t != ETH_ALEN)
890 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
891 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
892
893 if (t == ETH_ALEN)
894 ath79_set_mac_base(tmp);
895 else
896 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
897 "\"%s\"\n", mac_str);
898 }
899
900 static int __init ath79_ethaddr_setup(char *str)
901 {
902 ath79_parse_mac_addr(str);
903 return 1;
904 }
905 __setup("ethaddr=", ath79_ethaddr_setup);
906
907 static int __init ath79_kmac_setup(char *str)
908 {
909 ath79_parse_mac_addr(str);
910 return 1;
911 }
912 __setup("kmac=", ath79_kmac_setup);
913
914 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
915 int offset)
916 {
917 int t;
918
919 if (!is_valid_ether_addr(src)) {
920 memset(dst, '\0', ETH_ALEN);
921 return;
922 }
923
924 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
925 t += offset;
926
927 dst[0] = src[0];
928 dst[1] = src[1];
929 dst[2] = src[2];
930 dst[3] = (t >> 16) & 0xff;
931 dst[4] = (t >> 8) & 0xff;
932 dst[5] = t & 0xff;
933 }
934
935 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
936 {
937 int i;
938
939 if (!is_valid_ether_addr(src)) {
940 memset(dst, '\0', ETH_ALEN);
941 return;
942 }
943
944 for (i = 0; i < ETH_ALEN; i++)
945 dst[i] = src[i];
946 dst[0] |= 0x02;
947 }
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