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ar71xx: fixup allowed PHY interface types for QCA9558
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
26 #include <asm/mach-ath79/irq.h>
27
28 #include "common.h"
29 #include "dev-eth.h"
30
31 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
32
33 static struct resource ath79_mdio0_resources[] = {
34 {
35 .name = "mdio_base",
36 .flags = IORESOURCE_MEM,
37 .start = AR71XX_GE0_BASE,
38 .end = AR71XX_GE0_BASE + 0x200 - 1,
39 }
40 };
41
42 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
43
44 struct platform_device ath79_mdio0_device = {
45 .name = "ag71xx-mdio",
46 .id = 0,
47 .resource = ath79_mdio0_resources,
48 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
49 .dev = {
50 .platform_data = &ath79_mdio0_data,
51 },
52 };
53
54 static struct resource ath79_mdio1_resources[] = {
55 {
56 .name = "mdio_base",
57 .flags = IORESOURCE_MEM,
58 .start = AR71XX_GE1_BASE,
59 .end = AR71XX_GE1_BASE + 0x200 - 1,
60 }
61 };
62
63 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
64
65 struct platform_device ath79_mdio1_device = {
66 .name = "ag71xx-mdio",
67 .id = 1,
68 .resource = ath79_mdio1_resources,
69 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
70 .dev = {
71 .platform_data = &ath79_mdio1_data,
72 },
73 };
74
75 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
76 {
77 void __iomem *base;
78 u32 t;
79
80 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
81
82 t = __raw_readl(base + cfg_reg);
83 t &= ~(3 << shift);
84 t |= (2 << shift);
85 __raw_writel(t, base + cfg_reg);
86 udelay(100);
87
88 __raw_writel(pll_val, base + pll_reg);
89
90 t |= (3 << shift);
91 __raw_writel(t, base + cfg_reg);
92 udelay(100);
93
94 t &= ~(3 << shift);
95 __raw_writel(t, base + cfg_reg);
96 udelay(100);
97
98 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
99 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
100
101 iounmap(base);
102 }
103
104 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
105 unsigned int mii_if)
106 {
107 void __iomem *base;
108 u32 t;
109
110 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
111
112 t = __raw_readl(base + reg);
113 t &= ~(AR71XX_MII_CTRL_IF_MASK);
114 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
115 __raw_writel(t, base + reg);
116
117 iounmap(base);
118 }
119
120 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
121 {
122 void __iomem *base;
123 unsigned int mii_speed;
124 u32 t;
125
126 switch (speed) {
127 case SPEED_10:
128 mii_speed = AR71XX_MII_CTRL_SPEED_10;
129 break;
130 case SPEED_100:
131 mii_speed = AR71XX_MII_CTRL_SPEED_100;
132 break;
133 case SPEED_1000:
134 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
135 break;
136 default:
137 BUG();
138 }
139
140 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
141
142 t = __raw_readl(base + reg);
143 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
144 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
145 __raw_writel(t, base + reg);
146
147 iounmap(base);
148 }
149
150 static unsigned long ar934x_get_mdio_ref_clock(void)
151 {
152 void __iomem *base;
153 unsigned long ret;
154 u32 t;
155
156 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
157
158 ret = 0;
159 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
160 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
161 ret = 100 * 1000 * 1000;
162 } else {
163 struct clk *clk;
164
165 clk = clk_get(NULL, "ref");
166 if (!IS_ERR(clk))
167 ret = clk_get_rate(clk);
168 }
169
170 iounmap(base);
171
172 return ret;
173 }
174
175 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
176 {
177 struct platform_device *mdio_dev;
178 struct ag71xx_mdio_platform_data *mdio_data;
179 unsigned int max_id;
180
181 if (ath79_soc == ATH79_SOC_AR9341 ||
182 ath79_soc == ATH79_SOC_AR9342 ||
183 ath79_soc == ATH79_SOC_AR9344 ||
184 ath79_soc == ATH79_SOC_QCA9558)
185 max_id = 1;
186 else
187 max_id = 0;
188
189 if (id > max_id) {
190 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
191 return;
192 }
193
194 switch (ath79_soc) {
195 case ATH79_SOC_AR7241:
196 case ATH79_SOC_AR9330:
197 case ATH79_SOC_AR9331:
198 mdio_dev = &ath79_mdio1_device;
199 mdio_data = &ath79_mdio1_data;
200 break;
201
202 case ATH79_SOC_AR9341:
203 case ATH79_SOC_AR9342:
204 case ATH79_SOC_AR9344:
205 case ATH79_SOC_QCA9558:
206 if (id == 0) {
207 mdio_dev = &ath79_mdio0_device;
208 mdio_data = &ath79_mdio0_data;
209 } else {
210 mdio_dev = &ath79_mdio1_device;
211 mdio_data = &ath79_mdio1_data;
212 }
213 break;
214
215 case ATH79_SOC_AR7242:
216 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
217 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
218 AR71XX_ETH0_PLL_SHIFT);
219 /* fall through */
220 default:
221 mdio_dev = &ath79_mdio0_device;
222 mdio_data = &ath79_mdio0_data;
223 break;
224 }
225
226 mdio_data->phy_mask = phy_mask;
227
228 switch (ath79_soc) {
229 case ATH79_SOC_AR7240:
230 mdio_data->is_ar7240 = 1;
231 /* fall through */
232 case ATH79_SOC_AR7241:
233 mdio_data->builtin_switch = 1;
234 break;
235
236 case ATH79_SOC_AR9330:
237 mdio_data->is_ar9330 = 1;
238 /* fall through */
239 case ATH79_SOC_AR9331:
240 mdio_data->builtin_switch = 1;
241 break;
242
243 case ATH79_SOC_AR9341:
244 case ATH79_SOC_AR9342:
245 case ATH79_SOC_AR9344:
246 if (id == 1) {
247 mdio_data->builtin_switch = 1;
248 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
249 mdio_data->mdio_clock = 6250000;
250 }
251 mdio_data->is_ar934x = 1;
252 break;
253 case ATH79_SOC_QCA9558:
254 if (id == 1)
255 mdio_data->builtin_switch = 1;
256 mdio_data->is_ar934x = 1;
257 break;
258
259 default:
260 break;
261 }
262
263 platform_device_register(mdio_dev);
264 }
265
266 struct ath79_eth_pll_data ath79_eth0_pll_data;
267 struct ath79_eth_pll_data ath79_eth1_pll_data;
268
269 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
270 {
271 struct ath79_eth_pll_data *pll_data;
272 u32 pll_val;
273
274 switch (mac) {
275 case 0:
276 pll_data = &ath79_eth0_pll_data;
277 break;
278 case 1:
279 pll_data = &ath79_eth1_pll_data;
280 break;
281 default:
282 BUG();
283 }
284
285 switch (speed) {
286 case SPEED_10:
287 pll_val = pll_data->pll_10;
288 break;
289 case SPEED_100:
290 pll_val = pll_data->pll_100;
291 break;
292 case SPEED_1000:
293 pll_val = pll_data->pll_1000;
294 break;
295 default:
296 BUG();
297 }
298
299 return pll_val;
300 }
301
302 static void ath79_set_speed_ge0(int speed)
303 {
304 u32 val = ath79_get_eth_pll(0, speed);
305
306 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
307 val, AR71XX_ETH0_PLL_SHIFT);
308 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
309 }
310
311 static void ath79_set_speed_ge1(int speed)
312 {
313 u32 val = ath79_get_eth_pll(1, speed);
314
315 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
316 val, AR71XX_ETH1_PLL_SHIFT);
317 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
318 }
319
320 static void ar7242_set_speed_ge0(int speed)
321 {
322 u32 val = ath79_get_eth_pll(0, speed);
323 void __iomem *base;
324
325 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
326 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
327 iounmap(base);
328 }
329
330 static void ar91xx_set_speed_ge0(int speed)
331 {
332 u32 val = ath79_get_eth_pll(0, speed);
333
334 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
335 val, AR913X_ETH0_PLL_SHIFT);
336 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
337 }
338
339 static void ar91xx_set_speed_ge1(int speed)
340 {
341 u32 val = ath79_get_eth_pll(1, speed);
342
343 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
344 val, AR913X_ETH1_PLL_SHIFT);
345 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
346 }
347
348 static void ar934x_set_speed_ge0(int speed)
349 {
350 void __iomem *base;
351 u32 val = ath79_get_eth_pll(0, speed);
352
353 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
354 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
355 iounmap(base);
356 }
357
358 static void ath79_set_speed_dummy(int speed)
359 {
360 }
361
362 static void ath79_ddr_no_flush(void)
363 {
364 }
365
366 static void ath79_ddr_flush_ge0(void)
367 {
368 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
369 }
370
371 static void ath79_ddr_flush_ge1(void)
372 {
373 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
374 }
375
376 static void ar724x_ddr_flush_ge0(void)
377 {
378 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
379 }
380
381 static void ar724x_ddr_flush_ge1(void)
382 {
383 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
384 }
385
386 static void ar91xx_ddr_flush_ge0(void)
387 {
388 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
389 }
390
391 static void ar91xx_ddr_flush_ge1(void)
392 {
393 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
394 }
395
396 static void ar933x_ddr_flush_ge0(void)
397 {
398 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
399 }
400
401 static void ar933x_ddr_flush_ge1(void)
402 {
403 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
404 }
405
406 static struct resource ath79_eth0_resources[] = {
407 {
408 .name = "mac_base",
409 .flags = IORESOURCE_MEM,
410 .start = AR71XX_GE0_BASE,
411 .end = AR71XX_GE0_BASE + 0x200 - 1,
412 }, {
413 .name = "mac_irq",
414 .flags = IORESOURCE_IRQ,
415 .start = ATH79_CPU_IRQ_GE0,
416 .end = ATH79_CPU_IRQ_GE0,
417 },
418 };
419
420 struct ag71xx_platform_data ath79_eth0_data = {
421 .reset_bit = AR71XX_RESET_GE0_MAC,
422 };
423
424 struct platform_device ath79_eth0_device = {
425 .name = "ag71xx",
426 .id = 0,
427 .resource = ath79_eth0_resources,
428 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
429 .dev = {
430 .platform_data = &ath79_eth0_data,
431 },
432 };
433
434 static struct resource ath79_eth1_resources[] = {
435 {
436 .name = "mac_base",
437 .flags = IORESOURCE_MEM,
438 .start = AR71XX_GE1_BASE,
439 .end = AR71XX_GE1_BASE + 0x200 - 1,
440 }, {
441 .name = "mac_irq",
442 .flags = IORESOURCE_IRQ,
443 .start = ATH79_CPU_IRQ_GE1,
444 .end = ATH79_CPU_IRQ_GE1,
445 },
446 };
447
448 struct ag71xx_platform_data ath79_eth1_data = {
449 .reset_bit = AR71XX_RESET_GE1_MAC,
450 };
451
452 struct platform_device ath79_eth1_device = {
453 .name = "ag71xx",
454 .id = 1,
455 .resource = ath79_eth1_resources,
456 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
457 .dev = {
458 .platform_data = &ath79_eth1_data,
459 },
460 };
461
462 struct ag71xx_switch_platform_data ath79_switch_data;
463
464 #define AR71XX_PLL_VAL_1000 0x00110000
465 #define AR71XX_PLL_VAL_100 0x00001099
466 #define AR71XX_PLL_VAL_10 0x00991099
467
468 #define AR724X_PLL_VAL_1000 0x00110000
469 #define AR724X_PLL_VAL_100 0x00001099
470 #define AR724X_PLL_VAL_10 0x00991099
471
472 #define AR7242_PLL_VAL_1000 0x16000000
473 #define AR7242_PLL_VAL_100 0x00000101
474 #define AR7242_PLL_VAL_10 0x00001616
475
476 #define AR913X_PLL_VAL_1000 0x1a000000
477 #define AR913X_PLL_VAL_100 0x13000a44
478 #define AR913X_PLL_VAL_10 0x00441099
479
480 #define AR933X_PLL_VAL_1000 0x00110000
481 #define AR933X_PLL_VAL_100 0x00001099
482 #define AR933X_PLL_VAL_10 0x00991099
483
484 #define AR934X_PLL_VAL_1000 0x16000000
485 #define AR934X_PLL_VAL_100 0x00000101
486 #define AR934X_PLL_VAL_10 0x00001616
487
488 static void __init ath79_init_eth_pll_data(unsigned int id)
489 {
490 struct ath79_eth_pll_data *pll_data;
491 u32 pll_10, pll_100, pll_1000;
492
493 switch (id) {
494 case 0:
495 pll_data = &ath79_eth0_pll_data;
496 break;
497 case 1:
498 pll_data = &ath79_eth1_pll_data;
499 break;
500 default:
501 BUG();
502 }
503
504 switch (ath79_soc) {
505 case ATH79_SOC_AR7130:
506 case ATH79_SOC_AR7141:
507 case ATH79_SOC_AR7161:
508 pll_10 = AR71XX_PLL_VAL_10;
509 pll_100 = AR71XX_PLL_VAL_100;
510 pll_1000 = AR71XX_PLL_VAL_1000;
511 break;
512
513 case ATH79_SOC_AR7240:
514 case ATH79_SOC_AR7241:
515 pll_10 = AR724X_PLL_VAL_10;
516 pll_100 = AR724X_PLL_VAL_100;
517 pll_1000 = AR724X_PLL_VAL_1000;
518 break;
519
520 case ATH79_SOC_AR7242:
521 pll_10 = AR7242_PLL_VAL_10;
522 pll_100 = AR7242_PLL_VAL_100;
523 pll_1000 = AR7242_PLL_VAL_1000;
524 break;
525
526 case ATH79_SOC_AR9130:
527 case ATH79_SOC_AR9132:
528 pll_10 = AR913X_PLL_VAL_10;
529 pll_100 = AR913X_PLL_VAL_100;
530 pll_1000 = AR913X_PLL_VAL_1000;
531 break;
532
533 case ATH79_SOC_AR9330:
534 case ATH79_SOC_AR9331:
535 pll_10 = AR933X_PLL_VAL_10;
536 pll_100 = AR933X_PLL_VAL_100;
537 pll_1000 = AR933X_PLL_VAL_1000;
538 break;
539
540 case ATH79_SOC_AR9341:
541 case ATH79_SOC_AR9342:
542 case ATH79_SOC_AR9344:
543 case ATH79_SOC_QCA9558:
544 pll_10 = AR934X_PLL_VAL_10;
545 pll_100 = AR934X_PLL_VAL_100;
546 pll_1000 = AR934X_PLL_VAL_1000;
547 break;
548
549 default:
550 BUG();
551 }
552
553 if (!pll_data->pll_10)
554 pll_data->pll_10 = pll_10;
555
556 if (!pll_data->pll_100)
557 pll_data->pll_100 = pll_100;
558
559 if (!pll_data->pll_1000)
560 pll_data->pll_1000 = pll_1000;
561 }
562
563 static int __init ath79_setup_phy_if_mode(unsigned int id,
564 struct ag71xx_platform_data *pdata)
565 {
566 unsigned int mii_if;
567
568 switch (id) {
569 case 0:
570 switch (ath79_soc) {
571 case ATH79_SOC_AR7130:
572 case ATH79_SOC_AR7141:
573 case ATH79_SOC_AR7161:
574 case ATH79_SOC_AR9130:
575 case ATH79_SOC_AR9132:
576 switch (pdata->phy_if_mode) {
577 case PHY_INTERFACE_MODE_MII:
578 mii_if = AR71XX_MII0_CTRL_IF_MII;
579 break;
580 case PHY_INTERFACE_MODE_GMII:
581 mii_if = AR71XX_MII0_CTRL_IF_GMII;
582 break;
583 case PHY_INTERFACE_MODE_RGMII:
584 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
585 break;
586 case PHY_INTERFACE_MODE_RMII:
587 mii_if = AR71XX_MII0_CTRL_IF_RMII;
588 break;
589 default:
590 return -EINVAL;
591 }
592 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
593 break;
594
595 case ATH79_SOC_AR7240:
596 case ATH79_SOC_AR7241:
597 case ATH79_SOC_AR9330:
598 case ATH79_SOC_AR9331:
599 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
600 break;
601
602 case ATH79_SOC_AR7242:
603 /* FIXME */
604
605 case ATH79_SOC_AR9341:
606 case ATH79_SOC_AR9342:
607 case ATH79_SOC_AR9344:
608 switch (pdata->phy_if_mode) {
609 case PHY_INTERFACE_MODE_MII:
610 case PHY_INTERFACE_MODE_GMII:
611 case PHY_INTERFACE_MODE_RGMII:
612 case PHY_INTERFACE_MODE_RMII:
613 break;
614 default:
615 return -EINVAL;
616 }
617 break;
618
619 case ATH79_SOC_QCA9558:
620 switch (pdata->phy_if_mode) {
621 case PHY_INTERFACE_MODE_MII:
622 case PHY_INTERFACE_MODE_RGMII:
623 case PHY_INTERFACE_MODE_SGMII:
624 break;
625 default:
626 return -EINVAL;
627 }
628 break;
629
630 default:
631 BUG();
632 }
633 break;
634 case 1:
635 switch (ath79_soc) {
636 case ATH79_SOC_AR7130:
637 case ATH79_SOC_AR7141:
638 case ATH79_SOC_AR7161:
639 case ATH79_SOC_AR9130:
640 case ATH79_SOC_AR9132:
641 switch (pdata->phy_if_mode) {
642 case PHY_INTERFACE_MODE_RMII:
643 mii_if = AR71XX_MII1_CTRL_IF_RMII;
644 break;
645 case PHY_INTERFACE_MODE_RGMII:
646 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
647 break;
648 default:
649 return -EINVAL;
650 }
651 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
652 break;
653
654 case ATH79_SOC_AR7240:
655 case ATH79_SOC_AR7241:
656 case ATH79_SOC_AR9330:
657 case ATH79_SOC_AR9331:
658 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
659 break;
660
661 case ATH79_SOC_AR7242:
662 /* FIXME */
663
664 case ATH79_SOC_AR9341:
665 case ATH79_SOC_AR9342:
666 case ATH79_SOC_AR9344:
667 switch (pdata->phy_if_mode) {
668 case PHY_INTERFACE_MODE_MII:
669 case PHY_INTERFACE_MODE_GMII:
670 break;
671 default:
672 return -EINVAL;
673 }
674 break;
675
676 case ATH79_SOC_QCA9558:
677 switch (pdata->phy_if_mode) {
678 case PHY_INTERFACE_MODE_MII:
679 case PHY_INTERFACE_MODE_RGMII:
680 case PHY_INTERFACE_MODE_SGMII:
681 break;
682 default:
683 return -EINVAL;
684 }
685 break;
686
687 default:
688 BUG();
689 }
690 break;
691 }
692
693 return 0;
694 }
695
696 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
697 {
698 void __iomem *base;
699 u32 t;
700
701 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
702
703 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
704 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
705 if (mac)
706 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
707 if (mdio)
708 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
709 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
710
711 iounmap(base);
712 }
713
714 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
715 {
716 void __iomem *base;
717 u32 t;
718
719 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
720
721 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
722
723 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
724 AR934X_ETH_CFG_MII_GMAC0 |
725 AR934X_ETH_CFG_GMII_GMAC0 |
726 AR934X_ETH_CFG_SW_ONLY_MODE |
727 AR934X_ETH_CFG_SW_PHY_SWAP);
728
729 t |= mask;
730
731 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
732 /* flush write */
733 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
734
735 iounmap(base);
736 }
737
738 static int ath79_eth_instance __initdata;
739 void __init ath79_register_eth(unsigned int id)
740 {
741 struct platform_device *pdev;
742 struct ag71xx_platform_data *pdata;
743 int err;
744
745 if (id > 1) {
746 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
747 return;
748 }
749
750 ath79_init_eth_pll_data(id);
751
752 if (id == 0)
753 pdev = &ath79_eth0_device;
754 else
755 pdev = &ath79_eth1_device;
756
757 pdata = pdev->dev.platform_data;
758
759 err = ath79_setup_phy_if_mode(id, pdata);
760 if (err) {
761 printk(KERN_ERR
762 "ar71xx: invalid PHY interface mode for GE%u\n", id);
763 return;
764 }
765
766 switch (ath79_soc) {
767 case ATH79_SOC_AR7130:
768 if (id == 0) {
769 pdata->ddr_flush = ath79_ddr_flush_ge0;
770 pdata->set_speed = ath79_set_speed_ge0;
771 } else {
772 pdata->ddr_flush = ath79_ddr_flush_ge1;
773 pdata->set_speed = ath79_set_speed_ge1;
774 }
775 break;
776
777 case ATH79_SOC_AR7141:
778 case ATH79_SOC_AR7161:
779 if (id == 0) {
780 pdata->ddr_flush = ath79_ddr_flush_ge0;
781 pdata->set_speed = ath79_set_speed_ge0;
782 } else {
783 pdata->ddr_flush = ath79_ddr_flush_ge1;
784 pdata->set_speed = ath79_set_speed_ge1;
785 }
786 pdata->has_gbit = 1;
787 break;
788
789 case ATH79_SOC_AR7242:
790 if (id == 0) {
791 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
792 AR71XX_RESET_GE0_PHY;
793 pdata->ddr_flush = ar724x_ddr_flush_ge0;
794 pdata->set_speed = ar7242_set_speed_ge0;
795 } else {
796 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
797 AR71XX_RESET_GE1_PHY;
798 pdata->ddr_flush = ar724x_ddr_flush_ge1;
799 pdata->set_speed = ath79_set_speed_dummy;
800 }
801 pdata->has_gbit = 1;
802 pdata->is_ar724x = 1;
803
804 if (!pdata->fifo_cfg1)
805 pdata->fifo_cfg1 = 0x0010ffff;
806 if (!pdata->fifo_cfg2)
807 pdata->fifo_cfg2 = 0x015500aa;
808 if (!pdata->fifo_cfg3)
809 pdata->fifo_cfg3 = 0x01f00140;
810 break;
811
812 case ATH79_SOC_AR7241:
813 if (id == 0)
814 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
815 else
816 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
817 /* fall through */
818 case ATH79_SOC_AR7240:
819 if (id == 0) {
820 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
821 pdata->ddr_flush = ar724x_ddr_flush_ge0;
822 pdata->set_speed = ath79_set_speed_dummy;
823
824 pdata->phy_mask = BIT(4);
825 } else {
826 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
827 pdata->ddr_flush = ar724x_ddr_flush_ge1;
828 pdata->set_speed = ath79_set_speed_dummy;
829
830 pdata->speed = SPEED_1000;
831 pdata->duplex = DUPLEX_FULL;
832 pdata->switch_data = &ath79_switch_data;
833
834 ath79_switch_data.phy_poll_mask |= BIT(4);
835 }
836 pdata->has_gbit = 1;
837 pdata->is_ar724x = 1;
838 if (ath79_soc == ATH79_SOC_AR7240)
839 pdata->is_ar7240 = 1;
840
841 if (!pdata->fifo_cfg1)
842 pdata->fifo_cfg1 = 0x0010ffff;
843 if (!pdata->fifo_cfg2)
844 pdata->fifo_cfg2 = 0x015500aa;
845 if (!pdata->fifo_cfg3)
846 pdata->fifo_cfg3 = 0x01f00140;
847 break;
848
849 case ATH79_SOC_AR9130:
850 if (id == 0) {
851 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
852 pdata->set_speed = ar91xx_set_speed_ge0;
853 } else {
854 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
855 pdata->set_speed = ar91xx_set_speed_ge1;
856 }
857 pdata->is_ar91xx = 1;
858 break;
859
860 case ATH79_SOC_AR9132:
861 if (id == 0) {
862 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
863 pdata->set_speed = ar91xx_set_speed_ge0;
864 } else {
865 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
866 pdata->set_speed = ar91xx_set_speed_ge1;
867 }
868 pdata->is_ar91xx = 1;
869 pdata->has_gbit = 1;
870 break;
871
872 case ATH79_SOC_AR9330:
873 case ATH79_SOC_AR9331:
874 if (id == 0) {
875 pdata->reset_bit = AR933X_RESET_GE0_MAC |
876 AR933X_RESET_GE0_MDIO;
877 pdata->ddr_flush = ar933x_ddr_flush_ge0;
878 pdata->set_speed = ath79_set_speed_dummy;
879
880 pdata->phy_mask = BIT(4);
881 } else {
882 pdata->reset_bit = AR933X_RESET_GE1_MAC |
883 AR933X_RESET_GE1_MDIO;
884 pdata->ddr_flush = ar933x_ddr_flush_ge1;
885 pdata->set_speed = ath79_set_speed_dummy;
886
887 pdata->speed = SPEED_1000;
888 pdata->duplex = DUPLEX_FULL;
889 pdata->switch_data = &ath79_switch_data;
890
891 ath79_switch_data.phy_poll_mask |= BIT(4);
892 }
893
894 pdata->has_gbit = 1;
895 pdata->is_ar724x = 1;
896
897 if (!pdata->fifo_cfg1)
898 pdata->fifo_cfg1 = 0x0010ffff;
899 if (!pdata->fifo_cfg2)
900 pdata->fifo_cfg2 = 0x015500aa;
901 if (!pdata->fifo_cfg3)
902 pdata->fifo_cfg3 = 0x01f00140;
903 break;
904
905 case ATH79_SOC_AR9341:
906 case ATH79_SOC_AR9342:
907 case ATH79_SOC_AR9344:
908 case ATH79_SOC_QCA9558:
909 if (id == 0) {
910 pdata->reset_bit = AR934X_RESET_GE0_MAC |
911 AR934X_RESET_GE0_MDIO;
912 pdata->set_speed = ar934x_set_speed_ge0;
913 } else {
914 pdata->reset_bit = AR934X_RESET_GE1_MAC |
915 AR934X_RESET_GE1_MDIO;
916 pdata->set_speed = ath79_set_speed_dummy;
917
918 pdata->switch_data = &ath79_switch_data;
919
920 /* reset the built-in switch */
921 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
922 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
923 }
924
925 pdata->ddr_flush = ath79_ddr_no_flush;
926 pdata->has_gbit = 1;
927 pdata->is_ar724x = 1;
928
929 if (!pdata->fifo_cfg1)
930 pdata->fifo_cfg1 = 0x0010ffff;
931 if (!pdata->fifo_cfg2)
932 pdata->fifo_cfg2 = 0x015500aa;
933 if (!pdata->fifo_cfg3)
934 pdata->fifo_cfg3 = 0x01f00140;
935 break;
936
937 default:
938 BUG();
939 }
940
941 switch (pdata->phy_if_mode) {
942 case PHY_INTERFACE_MODE_GMII:
943 case PHY_INTERFACE_MODE_RGMII:
944 case PHY_INTERFACE_MODE_SGMII:
945 if (!pdata->has_gbit) {
946 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
947 id);
948 return;
949 }
950 /* fallthrough */
951 default:
952 break;
953 }
954
955 if (!is_valid_ether_addr(pdata->mac_addr)) {
956 random_ether_addr(pdata->mac_addr);
957 printk(KERN_DEBUG
958 "ar71xx: using random MAC address for eth%d\n",
959 ath79_eth_instance);
960 }
961
962 if (pdata->mii_bus_dev == NULL) {
963 switch (ath79_soc) {
964 case ATH79_SOC_AR9341:
965 case ATH79_SOC_AR9342:
966 case ATH79_SOC_AR9344:
967 if (id == 0)
968 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
969 else
970 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
971 break;
972
973 case ATH79_SOC_AR7241:
974 case ATH79_SOC_AR9330:
975 case ATH79_SOC_AR9331:
976 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
977 break;
978
979 case ATH79_SOC_QCA9558:
980 /* don't assign any MDIO device by default */
981 break;
982
983 default:
984 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
985 break;
986 }
987 }
988
989 /* Reset the device */
990 ath79_device_reset_set(pdata->reset_bit);
991 mdelay(100);
992
993 ath79_device_reset_clear(pdata->reset_bit);
994 mdelay(100);
995
996 platform_device_register(pdev);
997 ath79_eth_instance++;
998 }
999
1000 void __init ath79_set_mac_base(unsigned char *mac)
1001 {
1002 memcpy(ath79_mac_base, mac, ETH_ALEN);
1003 }
1004
1005 void __init ath79_parse_mac_addr(char *mac_str)
1006 {
1007 u8 tmp[ETH_ALEN];
1008 int t;
1009
1010 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1011 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1012
1013 if (t != ETH_ALEN)
1014 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1015 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1016
1017 if (t == ETH_ALEN)
1018 ath79_set_mac_base(tmp);
1019 else
1020 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
1021 "\"%s\"\n", mac_str);
1022 }
1023
1024 static int __init ath79_ethaddr_setup(char *str)
1025 {
1026 ath79_parse_mac_addr(str);
1027 return 1;
1028 }
1029 __setup("ethaddr=", ath79_ethaddr_setup);
1030
1031 static int __init ath79_kmac_setup(char *str)
1032 {
1033 ath79_parse_mac_addr(str);
1034 return 1;
1035 }
1036 __setup("kmac=", ath79_kmac_setup);
1037
1038 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1039 int offset)
1040 {
1041 int t;
1042
1043 if (!dst)
1044 return;
1045
1046 if (!src || !is_valid_ether_addr(src)) {
1047 memset(dst, '\0', ETH_ALEN);
1048 return;
1049 }
1050
1051 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1052 t += offset;
1053
1054 dst[0] = src[0];
1055 dst[1] = src[1];
1056 dst[2] = src[2];
1057 dst[3] = (t >> 16) & 0xff;
1058 dst[4] = (t >> 8) & 0xff;
1059 dst[5] = t & 0xff;
1060 }
1061
1062 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1063 {
1064 int i;
1065
1066 if (!dst)
1067 return;
1068
1069 if (!src || !is_valid_ether_addr(src)) {
1070 memset(dst, '\0', ETH_ALEN);
1071 return;
1072 }
1073
1074 for (i = 0; i < ETH_ALEN; i++)
1075 dst[i] = src[i];
1076 dst[0] |= 0x02;
1077 }
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