target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c

   1 /*
   2  * TP-LINK Archer C7/TL-WDR4900 v2 board support
   3  *
   4  * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (c) 2014 施康成 <tenninjas@tenninjas.ca>
   6  *
   7  * Based on the Qualcomm Atheros AP135/AP136 reference board support code
   8  *   Copyright (c) 2012 Qualcomm Atheros
   9  *
  10  * Permission to use, copy, modify, and/or distribute this software for any
  11  * purpose with or without fee is hereby granted, provided that the above
  12  * copyright notice and this permission notice appear in all copies.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  15  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  16  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  17  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  18  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  19  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  20  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/pci.h>
  25 #include <linux/phy.h>
  26 #include <linux/gpio.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/ath9k_platform.h>
  29 #include <linux/ar8216_platform.h>
  30
  31 #include <asm/mach-ath79/ar71xx_regs.h>
  32
  33 #include "common.h"
  34 #include "dev-ap9x-pci.h"
  35 #include "dev-eth.h"
  36 #include "dev-gpio-buttons.h"
  37 #include "dev-leds-gpio.h"
  38 #include "dev-m25p80.h"
  39 #include "dev-spi.h"
  40 #include "dev-usb.h"
  41 #include "dev-wmac.h"
  42 #include "machtypes.h"
  43 #include "pci.h"
  44
  45 #define ARCHER_C7_GPIO_LED_WLAN2G       12
  46 #define ARCHER_C7_GPIO_LED_SYSTEM       14
  47 #define ARCHER_C7_GPIO_LED_QSS          15
  48 #define ARCHER_C7_GPIO_LED_WLAN5G       17
  49 #define ARCHER_C7_GPIO_LED_USB1         18
  50 #define ARCHER_C7_GPIO_LED_USB2         19
  51
  52 #define ARCHER_C7_GPIO_BTN_RFKILL       13
  53 #define ARCHER_C7_GPIO_BTN_RESET        16
  54
  55 #define ARCHER_C7_GPIO_USB1_POWER       22
  56 #define ARCHER_C7_GPIO_USB2_POWER       21
  57
  58 #define ARCHER_C7_KEYS_POLL_INTERVAL    20      /* msecs */
  59 #define ARCHER_C7_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C7_KEYS_POLL_INTERVAL)
  60
  61 #define ARCHER_C7_WMAC_CALDATA_OFFSET   0x1000
  62 #define ARCHER_C7_PCIE_CALDATA_OFFSET   0x5000
  63
  64 static const char *archer_c7_part_probes[] = {
  65         "tp-link",
  66         NULL,
  67 };
  68
  69 static struct flash_platform_data archer_c7_flash_data = {
  70         .part_probes    = archer_c7_part_probes,
  71 };
  72
  73 static struct gpio_led archer_c7_leds_gpio[] __initdata = {
  74         {
  75                 .name           = "tp-link:blue:qss",
  76                 .gpio           = ARCHER_C7_GPIO_LED_QSS,
  77                 .active_low     = 1,
  78         },
  79         {
  80                 .name           = "tp-link:blue:system",
  81                 .gpio           = ARCHER_C7_GPIO_LED_SYSTEM,
  82                 .active_low     = 1,
  83         },
  84         {
  85                 .name           = "tp-link:blue:wlan2g",
  86                 .gpio           = ARCHER_C7_GPIO_LED_WLAN2G,
  87                 .active_low     = 1,
  88         },
  89         {
  90                 .name           = "tp-link:blue:wlan5g",
  91                 .gpio           = ARCHER_C7_GPIO_LED_WLAN5G,
  92                 .active_low     = 1,
  93         },
  94         {
  95                 .name           = "tp-link:green:usb1",
  96                 .gpio           = ARCHER_C7_GPIO_LED_USB1,
  97                 .active_low     = 1,
  98         },
  99         {
 100                 .name           = "tp-link:green:usb2",
 101                 .gpio           = ARCHER_C7_GPIO_LED_USB2,
 102                 .active_low     = 1,
 103         },
 104 };
 105
 106 static struct gpio_keys_button archer_c7_gpio_keys[] __initdata = {
 107         {
 108                 .desc           = "Reset button",
 109                 .type           = EV_KEY,
 110                 .code           = KEY_WPS_BUTTON,
 111                 .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
 112                 .gpio           = ARCHER_C7_GPIO_BTN_RESET,
 113                 .active_low     = 1,
 114         },
 115         {
 116                 .desc           = "RFKILL switch",
 117                 .type           = EV_SW,
 118                 .code           = KEY_RFKILL,
 119                 .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
 120                 .gpio           = ARCHER_C7_GPIO_BTN_RFKILL,
 121         },
 122 };
 123
 124 static const struct ar8327_led_info archer_c7_leds_ar8327[] __initconst = {
 125         AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"),
 126         AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"),
 127         AR8327_LED_INFO(PHY2_0, HW, "tp-link:blue:lan2"),
 128         AR8327_LED_INFO(PHY3_0, HW, "tp-link:blue:lan3"),
 129         AR8327_LED_INFO(PHY4_0, HW, "tp-link:blue:lan4"),
 130 };
 131
 132 /* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */
 133 static struct ar8327_pad_cfg archer_c7_ar8327_pad0_cfg = {
 134         .mode = AR8327_PAD_MAC_SGMII,
 135         .sgmii_delay_en = true,
 136 };
 137
 138 /* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */
 139 static struct ar8327_pad_cfg archer_c7_ar8327_pad6_cfg = {
 140         .mode = AR8327_PAD_MAC_RGMII,
 141         .txclk_delay_en = true,
 142         .rxclk_delay_en = true,
 143         .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
 144         .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
 145 };
 146
 147 static struct ar8327_led_cfg archer_c7_ar8327_led_cfg = {
 148         .led_ctrl0 = 0xc737c737,
 149         .led_ctrl1 = 0x00000000,
 150         .led_ctrl2 = 0x00000000,
 151         .led_ctrl3 = 0x0030c300,
 152         .open_drain = false,
 153 };
 154
 155 static struct ar8327_platform_data archer_c7_ar8327_data = {
 156         .pad0_cfg = &archer_c7_ar8327_pad0_cfg,
 157         .pad6_cfg = &archer_c7_ar8327_pad6_cfg,
 158         .port0_cfg = {
 159                 .force_link = 1,
 160                 .speed = AR8327_PORT_SPEED_1000,
 161                 .duplex = 1,
 162                 .txpause = 1,
 163                 .rxpause = 1,
 164         },
 165         .port6_cfg = {
 166                 .force_link = 1,
 167                 .speed = AR8327_PORT_SPEED_1000,
 168                 .duplex = 1,
 169                 .txpause = 1,
 170                 .rxpause = 1,
 171         },
 172         .led_cfg = &archer_c7_ar8327_led_cfg,
 173         .num_leds = ARRAY_SIZE(archer_c7_leds_ar8327),
 174         .leds = archer_c7_leds_ar8327,
 175 };
 176
 177 static struct mdio_board_info archer_c7_mdio0_info[] = {
 178         {
 179                 .bus_id = "ag71xx-mdio.0",
 180                 .phy_addr = 0,
 181                 .platform_data = &archer_c7_ar8327_data,
 182         },
 183 };
 184
 185 static void __init common_setup(bool pcie_slot)
 186 {
 187         u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
 188         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 189         u8 tmpmac[ETH_ALEN];
 190
 191         ath79_register_m25p80(&archer_c7_flash_data);
 192         ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio),
 193                                  archer_c7_leds_gpio);
 194         ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL,
 195                                         ARRAY_SIZE(archer_c7_gpio_keys),
 196                                         archer_c7_gpio_keys);
 197
 198         ath79_init_mac(tmpmac, mac, -1);
 199         ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac);
 200
 201         if (pcie_slot) {
 202                 ath79_register_pci();
 203         } else {
 204                 ath79_init_mac(tmpmac, mac, -1);
 205                 ap9x_pci_setup_wmac_led_pin(0, 0);
 206                 ap91_pci_init(art + ARCHER_C7_PCIE_CALDATA_OFFSET, tmpmac);
 207         }
 208
 209         mdiobus_register_board_info(archer_c7_mdio0_info,
 210                                     ARRAY_SIZE(archer_c7_mdio0_info));
 211         ath79_register_mdio(0, 0x0);
 212
 213         ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
 214
 215         /* GMAC0 is connected to the RMGII interface */
 216         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 217         ath79_eth0_data.phy_mask = BIT(0);
 218         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 219         ath79_eth0_pll_data.pll_1000 = 0x56000000;
 220
 221         ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
 222         ath79_register_eth(0);
 223
 224         /* GMAC1 is connected to the SGMII interface */
 225         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
 226         ath79_eth1_data.speed = SPEED_1000;
 227         ath79_eth1_data.duplex = DUPLEX_FULL;
 228         ath79_eth1_pll_data.pll_1000 = 0x03000101;
 229
 230         ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
 231         ath79_register_eth(1);
 232
 233         gpio_request_one(ARCHER_C7_GPIO_USB1_POWER,
 234                          GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
 235                          "USB1 power");
 236         gpio_request_one(ARCHER_C7_GPIO_USB2_POWER,
 237                          GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
 238                          "USB2 power");
 239         ath79_register_usb();
 240 }
 241
 242 static void __init archer_c7_setup(void)
 243 {
 244         common_setup(true);
 245 }
 246
 247 MIPS_MACHINE(ATH79_MACH_ARCHER_C7, "ARCHER-C7", "TP-LINK Archer C7",
 248              archer_c7_setup);
 249
 250 static void __init tl_wdr4900_v2_setup(void)
 251 {
 252         common_setup(false);
 253 }
 254
 255 MIPS_MACHINE(ATH79_MACH_TL_WDR4900_V2, "TL-WDR4900-v2", "TP-LINK TL-WDR4900 v2",
 256              tl_wdr4900_v2_setup)
 257