[ar71xx] use enum for the machine type
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h
1 /*
2 * Atheros AR71xx SoC specific definitions
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __ASM_MACH_AR71XX_H
15 #define __ASM_MACH_AR71XX_H
16
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/bitops.h>
21
22 #ifndef __ASSEMBLER__
23
24 #define AR71XX_PCI_MEM_BASE 0x10000000
25 #define AR71XX_PCI_MEM_SIZE 0x08000000
26 #define AR71XX_APB_BASE 0x18000000
27 #define AR71XX_GE0_BASE 0x19000000
28 #define AR71XX_GE0_SIZE 0x01000000
29 #define AR71XX_GE1_BASE 0x1a000000
30 #define AR71XX_GE1_SIZE 0x01000000
31 #define AR71XX_EHCI_BASE 0x1b000000
32 #define AR71XX_EHCI_SIZE 0x01000000
33 #define AR71XX_OHCI_BASE 0x1c000000
34 #define AR71XX_OHCI_SIZE 0x01000000
35 #define AR71XX_SPI_BASE 0x1f000000
36 #define AR71XX_SPI_SIZE 0x01000000
37
38 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
39 #define AR71XX_DDR_CTRL_SIZE 0x10000
40 #define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
41 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
42 #define AR71XX_UART_SIZE 0x10000
43 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
44 #define AR71XX_USB_CTRL_SIZE 0x10000
45 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
46 #define AR71XX_GPIO_SIZE 0x10000
47 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
48 #define AR71XX_PLL_SIZE 0x10000
49 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
50 #define AR71XX_RESET_SIZE 0x10000
51 #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
52 #define AR71XX_MII_SIZE 0x10000
53 #define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
54 #define AR71XX_SLIC_SIZE 0x10000
55 #define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
56 #define AR71XX_DMA_SIZE 0x10000
57 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
58 #define AR71XX_STEREO_SIZE 0x10000
59 #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
60 #define AR91XX_WMAC_SIZE 0x30000
61
62 #define AR71XX_MEM_SIZE_MIN 0x0200000
63 #define AR71XX_MEM_SIZE_MAX 0x10000000
64
65 #define AR71XX_CPU_IRQ_BASE 0
66 #define AR71XX_MISC_IRQ_BASE 8
67 #define AR71XX_MISC_IRQ_COUNT 8
68 #define AR71XX_GPIO_IRQ_BASE 16
69 #define AR71XX_GPIO_IRQ_COUNT 16
70 #define AR71XX_PCI_IRQ_BASE 32
71 #define AR71XX_PCI_IRQ_COUNT 4
72
73 #define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2)
74 #define AR71XX_CPU_IRQ_WMAC (AR71XX_CPU_IRQ_BASE + 2)
75 #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
76 #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
77 #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
78 #define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
79 #define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
80
81 #define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
82 #define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
83 #define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
84 #define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
85 #define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
86 #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
87 #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
88 #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
89
90 #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
91
92 #define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
93 #define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
94 #define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
95 #define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 3)
96
97 extern u32 ar71xx_ahb_freq;
98 extern u32 ar71xx_cpu_freq;
99 extern u32 ar71xx_ddr_freq;
100
101 enum ar71xx_soc_type {
102 AR71XX_SOC_UNKNOWN,
103 AR71XX_SOC_AR7130,
104 AR71XX_SOC_AR7141,
105 AR71XX_SOC_AR7161,
106 AR71XX_SOC_AR9130,
107 AR71XX_SOC_AR9132
108 };
109
110 extern enum ar71xx_soc_type ar71xx_soc;
111
112 enum ar71xx_mach_type {
113 AR71XX_MACH_GENERIC = 0,
114 AR71XX_MACH_AP81, /* Atheros AP81 */
115 AR71XX_MACH_AP83, /* Atheros AP83 */
116 AR71XX_MACH_AW_NR580, /* AzureWave AW-NR580 */
117 AR71XX_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */
118 AR71XX_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */
119 AR71XX_MACH_RB_450, /* MikroTik RouterBOARD 450 */
120 AR71XX_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */
121 AR71XX_MACH_PB42, /* Atheros PB42 */
122 AR71XX_MACH_PB44, /* Atheros PB44 */
123 AR71XX_MACH_MZK_W04NU, /* Planex MZK-W04NU */
124 AR71XX_MACH_MZK_W300NH, /* Planex MZK-W300NH */
125 AR71XX_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */
126 AR71XX_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */
127 AR71XX_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */
128 AR71XX_MACH_UBNT_LSX, /* Ubiquiti LSX */
129 AR71XX_MACH_UBNT_RS, /* Ubiquiti RouterStation */
130 AR71XX_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */
131 AR71XX_MACH_WNR2000, /* NETGEAR WNR2000 */
132 AR71XX_MACH_WP543, /* Compex WP543 */
133 AR71XX_MACH_WRT160NL, /* Linksys WRT160NL */
134 AR71XX_MACH_WRT400N, /* Linksys WRT400N */
135 };
136
137 extern enum ar71xx_mach_type ar71xx_mach;
138
139 /*
140 * PLL block
141 */
142 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
143 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
144 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
145 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
146
147 #define AR71XX_PLL_DIV_SHIFT 3
148 #define AR71XX_PLL_DIV_MASK 0x1f
149 #define AR71XX_CPU_DIV_SHIFT 16
150 #define AR71XX_CPU_DIV_MASK 0x3
151 #define AR71XX_DDR_DIV_SHIFT 18
152 #define AR71XX_DDR_DIV_MASK 0x3
153 #define AR71XX_AHB_DIV_SHIFT 20
154 #define AR71XX_AHB_DIV_MASK 0x7
155
156 #define AR71XX_ETH0_PLL_SHIFT 17
157 #define AR71XX_ETH1_PLL_SHIFT 19
158
159 #define AR91XX_PLL_REG_CPU_CONFIG 0x00
160 #define AR91XX_PLL_REG_ETH_CONFIG 0x04
161 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
162 #define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
163
164 #define AR91XX_PLL_DIV_SHIFT 0
165 #define AR91XX_PLL_DIV_MASK 0x3ff
166 #define AR91XX_DDR_DIV_SHIFT 22
167 #define AR91XX_DDR_DIV_MASK 0x3
168 #define AR91XX_AHB_DIV_SHIFT 19
169 #define AR91XX_AHB_DIV_MASK 0x1
170
171 #define AR91XX_ETH0_PLL_SHIFT 20
172 #define AR91XX_ETH1_PLL_SHIFT 22
173
174 extern void __iomem *ar71xx_pll_base;
175
176 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
177 {
178 __raw_writel(val, ar71xx_pll_base + reg);
179 }
180
181 static inline u32 ar71xx_pll_rr(unsigned reg)
182 {
183 return __raw_readl(ar71xx_pll_base + reg);
184 }
185
186 /*
187 * USB_CONFIG block
188 */
189 #define USB_CTRL_REG_FLADJ 0x00
190 #define USB_CTRL_REG_CONFIG 0x04
191
192 extern void __iomem *ar71xx_usb_ctrl_base;
193
194 static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
195 {
196 __raw_writel(val, ar71xx_usb_ctrl_base + reg);
197 }
198
199 static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
200 {
201 return __raw_readl(ar71xx_usb_ctrl_base + reg);
202 }
203
204 /*
205 * GPIO block
206 */
207 #define GPIO_REG_OE 0x00
208 #define GPIO_REG_IN 0x04
209 #define GPIO_REG_OUT 0x08
210 #define GPIO_REG_SET 0x0c
211 #define GPIO_REG_CLEAR 0x10
212 #define GPIO_REG_INT_MODE 0x14
213 #define GPIO_REG_INT_TYPE 0x18
214 #define GPIO_REG_INT_POLARITY 0x1c
215 #define GPIO_REG_INT_PENDING 0x20
216 #define GPIO_REG_INT_ENABLE 0x24
217 #define GPIO_REG_FUNC 0x28
218
219 #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
220 #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
221 #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
222 #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
223 #define AR71XX_GPIO_FUNC_UART_EN BIT(8)
224 #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
225 #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
226
227 #define AR71XX_GPIO_COUNT 16
228
229 #define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22)
230 #define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
231 #define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20)
232 #define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19)
233 #define AR91XX_GPIO_FUNC_I2S1_EN BIT(18)
234 #define AR91XX_GPIO_FUNC_I2S0_EN BIT(17)
235 #define AR91XX_GPIO_FUNC_SLIC_EN BIT(16)
236 #define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
237 #define AR91XX_GPIO_FUNC_UART_EN BIT(8)
238 #define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4)
239
240 #define AR91XX_GPIO_COUNT 22
241
242 extern void __iomem *ar71xx_gpio_base;
243
244 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
245 {
246 __raw_writel(value, ar71xx_gpio_base + reg);
247 }
248
249 static inline u32 ar71xx_gpio_rr(unsigned reg)
250 {
251 return __raw_readl(ar71xx_gpio_base + reg);
252 }
253
254 void ar71xx_gpio_init(void) __init;
255 void ar71xx_gpio_function_enable(u32 mask);
256 void ar71xx_gpio_function_disable(u32 mask);
257
258 /*
259 * DDR_CTRL block
260 */
261 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
262 #define AR71XX_DDR_REG_PCI_WIN1 0x80
263 #define AR71XX_DDR_REG_PCI_WIN2 0x84
264 #define AR71XX_DDR_REG_PCI_WIN3 0x88
265 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
266 #define AR71XX_DDR_REG_PCI_WIN5 0x90
267 #define AR71XX_DDR_REG_PCI_WIN6 0x94
268 #define AR71XX_DDR_REG_PCI_WIN7 0x98
269 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
270 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
271 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
272 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
273
274 #define AR91XX_DDR_REG_FLUSH_GE0 0x7c
275 #define AR91XX_DDR_REG_FLUSH_GE1 0x80
276 #define AR91XX_DDR_REG_FLUSH_USB 0x84
277 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88
278
279 #define PCI_WIN0_OFFS 0x10000000
280 #define PCI_WIN1_OFFS 0x11000000
281 #define PCI_WIN2_OFFS 0x12000000
282 #define PCI_WIN3_OFFS 0x13000000
283 #define PCI_WIN4_OFFS 0x14000000
284 #define PCI_WIN5_OFFS 0x15000000
285 #define PCI_WIN6_OFFS 0x16000000
286 #define PCI_WIN7_OFFS 0x07000000
287
288 extern void __iomem *ar71xx_ddr_base;
289
290 static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
291 {
292 __raw_writel(val, ar71xx_ddr_base + reg);
293 }
294
295 static inline u32 ar71xx_ddr_rr(unsigned reg)
296 {
297 return __raw_readl(ar71xx_ddr_base + reg);
298 }
299
300 void ar71xx_ddr_flush(u32 reg);
301
302 /*
303 * PCI block
304 */
305 #define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
306 #define AR71XX_PCI_CFG_SIZE 0x100
307
308 #define PCI_REG_CRP_AD_CBE 0x00
309 #define PCI_REG_CRP_WRDATA 0x04
310 #define PCI_REG_CRP_RDDATA 0x08
311 #define PCI_REG_CFG_AD 0x0c
312 #define PCI_REG_CFG_CBE 0x10
313 #define PCI_REG_CFG_WRDATA 0x14
314 #define PCI_REG_CFG_RDDATA 0x18
315 #define PCI_REG_PCI_ERR 0x1c
316 #define PCI_REG_PCI_ERR_ADDR 0x20
317 #define PCI_REG_AHB_ERR 0x24
318 #define PCI_REG_AHB_ERR_ADDR 0x28
319
320 #define PCI_CRP_CMD_WRITE 0x00010000
321 #define PCI_CRP_CMD_READ 0x00000000
322 #define PCI_CFG_CMD_READ 0x0000000a
323 #define PCI_CFG_CMD_WRITE 0x0000000b
324
325 #define PCI_IDSEL_ADL_START 17
326
327 /*
328 * RESET block
329 */
330 #define AR71XX_RESET_REG_TIMER 0x00
331 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
332 #define AR71XX_RESET_REG_WDOG_CTRL 0x08
333 #define AR71XX_RESET_REG_WDOG 0x0c
334 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
335 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
336 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
337 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
338 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
339 #define AR71XX_RESET_REG_RESET_MODULE 0x24
340 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
341 #define AR71XX_RESET_REG_PERFC0 0x30
342 #define AR71XX_RESET_REG_PERFC1 0x34
343 #define AR71XX_RESET_REG_REV_ID 0x90
344
345 #define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
346 #define AR91XX_RESET_REG_RESET_MODULE 0x1c
347 #define AR91XX_RESET_REG_PERF_CTRL 0x20
348 #define AR91XX_RESET_REG_PERFC0 0x24
349 #define AR91XX_RESET_REG_PERFC1 0x28
350
351 #define WDOG_CTRL_LAST_RESET BIT(31)
352 #define WDOG_CTRL_ACTION_MASK 3
353 #define WDOG_CTRL_ACTION_NONE 0 /* no action */
354 #define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
355 #define WDOG_CTRL_ACTION_NMI 2 /* NMI */
356 #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
357
358 #define MISC_INT_DMA BIT(7)
359 #define MISC_INT_OHCI BIT(6)
360 #define MISC_INT_PERFC BIT(5)
361 #define MISC_INT_WDOG BIT(4)
362 #define MISC_INT_UART BIT(3)
363 #define MISC_INT_GPIO BIT(2)
364 #define MISC_INT_ERROR BIT(1)
365 #define MISC_INT_TIMER BIT(0)
366
367 #define PCI_INT_CORE BIT(4)
368 #define PCI_INT_DEV2 BIT(2)
369 #define PCI_INT_DEV1 BIT(1)
370 #define PCI_INT_DEV0 BIT(0)
371
372 #define RESET_MODULE_EXTERNAL BIT(28)
373 #define RESET_MODULE_FULL_CHIP BIT(24)
374 #define RESET_MODULE_AMBA2WMAC BIT(22)
375 #define RESET_MODULE_CPU_NMI BIT(21)
376 #define RESET_MODULE_CPU_COLD BIT(20)
377 #define RESET_MODULE_DMA BIT(19)
378 #define RESET_MODULE_SLIC BIT(18)
379 #define RESET_MODULE_STEREO BIT(17)
380 #define RESET_MODULE_DDR BIT(16)
381 #define RESET_MODULE_GE1_MAC BIT(13)
382 #define RESET_MODULE_GE1_PHY BIT(12)
383 #define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
384 #define RESET_MODULE_GE0_MAC BIT(9)
385 #define RESET_MODULE_GE0_PHY BIT(8)
386 #define RESET_MODULE_USB_OHCI_DLL BIT(6)
387 #define RESET_MODULE_USB_HOST BIT(5)
388 #define RESET_MODULE_USB_PHY BIT(4)
389 #define RESET_MODULE_PCI_BUS BIT(1)
390 #define RESET_MODULE_PCI_CORE BIT(0)
391
392 #define REV_ID_MASK 0xff
393 #define REV_ID_CHIP_MASK 0xf3
394 #define REV_ID_CHIP_AR7130 0xa0
395 #define REV_ID_CHIP_AR7141 0xa1
396 #define REV_ID_CHIP_AR7161 0xa2
397 #define REV_ID_CHIP_AR9130 0xb0
398 #define REV_ID_CHIP_AR9132 0xb1
399
400 #define REV_ID_REVISION_MASK 0x3
401 #define REV_ID_REVISION_SHIFT 2
402
403 extern void __iomem *ar71xx_reset_base;
404
405 static inline void ar71xx_reset_wr(unsigned reg, u32 val)
406 {
407 __raw_writel(val, ar71xx_reset_base + reg);
408 }
409
410 static inline u32 ar71xx_reset_rr(unsigned reg)
411 {
412 return __raw_readl(ar71xx_reset_base + reg);
413 }
414
415 void ar71xx_device_stop(u32 mask);
416 void ar71xx_device_start(u32 mask);
417
418 /*
419 * SPI block
420 */
421 #define SPI_REG_FS 0x00 /* Function Select */
422 #define SPI_REG_CTRL 0x04 /* SPI Control */
423 #define SPI_REG_IOC 0x08 /* SPI I/O Control */
424 #define SPI_REG_RDS 0x0c /* Read Data Shift */
425
426 #define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
427
428 #define SPI_CTRL_RD BIT(6) /* Remap Disable */
429 #define SPI_CTRL_DIV_MASK 0x3f
430
431 #define SPI_IOC_DO BIT(0) /* Data Out pin */
432 #define SPI_IOC_CLK BIT(8) /* CLK pin */
433 #define SPI_IOC_CS(n) BIT(16 + (n))
434 #define SPI_IOC_CS0 SPI_IOC_CS(0)
435 #define SPI_IOC_CS1 SPI_IOC_CS(1)
436 #define SPI_IOC_CS2 SPI_IOC_CS(2)
437 #define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
438
439 void ar71xx_flash_acquire(void);
440 void ar71xx_flash_release(void);
441
442 /*
443 * MII_CTRL block
444 */
445 #define MII_REG_MII0_CTRL 0x00
446 #define MII_REG_MII1_CTRL 0x04
447
448 #define MII0_CTRL_IF_GMII 0
449 #define MII0_CTRL_IF_MII 1
450 #define MII0_CTRL_IF_RGMII 2
451 #define MII0_CTRL_IF_RMII 3
452
453 #define MII1_CTRL_IF_RGMII 0
454 #define MII1_CTRL_IF_RMII 1
455
456 #endif /* __ASSEMBLER__ */
457
458 #endif /* __ASM_MACH_AR71XX_H */